DM54LS165 DM74LS165 8-Bit Parallel In Serial Output Shift Registers
May 1992
DM54LS165 DM74LS165 8-Bit Parallel
In Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data in
the direction of Q
A
toward Q
H
when clocked Parallel-in ac-
cess is made available by eight individual direct data inputs
which are enabled by a low level at the shift load input
These registers also feature gated clock inputs and comple-
mentary outputs from the eighth bit
Clocking is accomplished through a 2-input NOR gate per-
mitting one input to be used as a clock-inhibit function Hold-
ing either of the clock inputs high inhibits clocking and hold-
ing either clock input low with the load input high enables
the other clock input The clock-inhibit input should be
changed to the high level only while the clock input is high
Parallel loading is inhibited as long as the load input is high
Data at the parallel inputs are loaded directly into the regis-
ter on a high-to-low transition of the shift load input regard-
less of the logic levels on the clock clock inhibit or serial
inputs
Features
Y
Y
Y
Y
Y
Y
Complementary outputs
Direct overriding (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Typical frequency 35 MHz
Typical power dissipation 105 mW
Connection Diagram
Dual-In-Line Package
TL F 6399 鈥?
Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N
See NS Package Number J16A M16B N16E or W16A
Function Table
Inputs
Shift
Load
L
H
H
H
H
Clock
Inhibit
X
L
L
L
H
Clock
X
L
Serial
X
X
H
L
X
Parallel
A H
a h
X
X
X
X
Q
A
a
Q
A0
H
L
Q
A0
Internal
Outputs
Q
B
b
Q
B0
Q
An
Q
An
Q
B0
Output
Q
H
h
Q
H0
Q
Gn
Q
Gn
Q
H0
u
u
X
H
e
High Level (steady state) L
e
Low Level (steady state)
X
e
Don鈥檛 Care (any input including transitions)
u
e
Transition from low-to-high level
a h
e
The level of steady-state input at inputs A through H respectively
Q
A0
Q
B0
Q
H0
e
The level of Q
A
Q
B
or Q
H
respectively before the indicated steady-state input conditions were established
Q
An
Q
Gn
e
The level of Q
A
or Q
G
respectively before the most recent
transition of the clock
u
C
1995 National Semiconductor Corporation
TL F 6399
RRD-B30M105 Printed in U S A
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