DM74LS155 鈥?DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers
August 1986
Revised April 2000
DM74LS155 鈥?DM74LS156
Dual 2-Line to 4-Line Decoders/Demultiplexers
General Description
These TTL circuits feature dual 1-line-to-4-line demultiplex-
ers with individual strobes and common binary-address
inputs in a single 16-pin package. When both sections are
enabled by the strobes, the common address inputs
sequentially select and route associated input data to the
appropriate output of each section. The individual strobes
permit activating or inhibiting each of the 4-bit sections as
desired. Data applied to input C1 is inverted at its outputs
and data applied at C2 is true through its outputs. The
inverter following the C1 data input permits use as a 3-to-8-
line decoder, or 1-to-8-line demultiplexer, without external
gating. Input clamping diodes are provided on these cir-
cuits to minimize transmission-line effects and simplify sys-
tem design.
Features
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Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
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Individual strobes simplify cascading for decoding or
demultiplexing larger words
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Input clamping diodes simplify system design
s
Choice of outputs:
Totem-pole (DM74LS155)
Open-collector (DM74LS156)
Ordering Code:
Order Number
DM74LS155M
DM74LS155N
DM74LS156M
DM74LS156N
Package Number
M16A
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS006395
www.fairchildsemi.com
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