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DM74LS109AM Datasheet

  • DM74LS109AM

  • Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clea...

  • 5頁

  • FAIRCHILD

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DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
June 1986
Revised March 2000
DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flop with
Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge
of the clock. The data on the J and K inputs may be
changed while the clock is HIGH or LOW as long as setup
and hold times are not violated. A low logic level on the
preset or clear inputs will set or reset the outputs regard-
less of the logic levels of the other inputs.
Ordering Code:
Order Number
DM74LS109AM
DM74LS109AN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
鈫?/div>
鈫?/div>
鈫?/div>
鈫?/div>
L
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
0
H
Q
0
Q
H
L
L
Toggle
Q
0
L
Q
0
Outputs
Q
L
H
H
H (Note 1) H (Note 1)
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
鈫?=
Rising Edge of Pulse
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each active transition of the clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when pre-
set and/or clear inputs return to their inactive (HIGH) state.
漏 2000 Fairchild Semiconductor Corporation
DS006368
www.fairchildsemi.com

DM74LS109AM 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 2

  • 74LS

  • J-K Positive Edge Triggered Flip-Flop

  • Inverting/Non-Inverting

  • Single-Ended

  • 35 ns

  • - 0.4 mA

  • 5.25 V

  • + 70 C

  • SMD/SMT

  • SOIC-16

  • Rail

  • 0 C

  • 2

  • 1

  • 4.75 V

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