DM74ALS645A Octal Bus Transceivers
March 1987
Revised February 2000
DM74ALS645A
Octal Bus Transceivers
General Description
These octal bus transceivers are designed for asynchro-
nous two-way communication between data busses. These
devices transmit data from the A bus to the B bus or from
the B bus to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G) can be
used to disable the device so the busses are effectively
isolated.
Features
s
Advanced Oxide-isolated Ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Switching performance specified at 50 pF
s
PNP input design reduces input loading
Ordering Code:
Order Number
DM74ALS645AWM
DM74ALS645AN
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Logic Diagram
Function Table
Control
Inputs
G
L
L
H
DIR
L
H
X
B Data to A Bus
A Data to B Bus
Isolation
Operation
L
=
LOW Logic Level
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
漏 2000 Fairchild Semiconductor Corporation
DS009304
www.fairchildsemi.com
1
2
3
4
