DM74ALS245A Octal 3-STATE Bus Transceiver
September 1986
Revised February 2000
DM74ALS245A
Octal 3-STATE Bus Transceiver
General Description
This advanced low power Schottky device contains 8 pairs
of 3-STATE logic elements configured as octal bus trans-
ceivers. These circuits are designed for use in memory,
microprocessor systems and in asynchronous bidirectional
data buses. Two way communication between buses is
controlled by the (DIR) input. Data transmits either from the
A bus to the B bus or from the B bus to the A bus. Both the
driver and receiver outputs can be disabled via the (G)
enable input which causes outputs to enter the high imped-
ance mode so that the buses are effectively isolated.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Non-inverting logic output
s
Glitch free bus during power up and down
s
3-STATE outputs independently controlled on A and B
buses
s
Low output impedance to drive terminated transmission
lines to 133鈩?/div>
s
Switching response specified into 500鈩?50 pF
s
Specified to interface with CMOS at V
OH
=
V
CC
鈭?/div>
2V
s
PNP inputs to reduce input loading
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
Ordering Code:
Order Number
DM74ALS245AWM
DM74ALS245ASJ
DM74ALS245AMSA
DM74ALS245AN
Package Number
M20B
M20D
MSA20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Function Table
Control
Inputs
G
L
L
H
DIR
L
H
X
B Data to A Bus
A Data to B Bus
Hi-Z
Operation
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either HIGH or LOW Logic Level
漏 2000 Fairchild Semiconductor Corporation
DS006213
www.fairchildsemi.com
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