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DM7490A Datasheet

  • DM7490A

  • Decade and Binary Counters

  • 5頁

  • FAIRCHILD

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DM7490A Decade and Binary Counters
August 1986
Revised March 2000
DM7490A
Decade and Binary Counters
General Description
The DM7490A monolithic counter contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated set-
to-nine inputs for use in BCD nine鈥檚 complement applica-
tions.
To use the maximum count length (decade or four-bit
binary), the B input is connected to the Q
A
output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate Function Table. A sym-
metrical divide-by-ten count can be obtained from the
counters by connecting the Q
D
output to the A input and
applying the input count to the B input which gives a divide-
by-ten square wave at output Q
A
.
Features
s
Typical power dissipation
145 mW
s
Count frequency 42 MHz
Ordering Code:
Order Number
DM7490AN
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
漏 2000 Fairchild Semiconductor Corporation
DS006533
www.fairchildsemi.com

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