DM54194 4-Bit Bidirectional Universal Shift Registers
June 1989
DM54194
4-Bit Bidirectional Universal Shift Registers
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register it features parallel inputs parallel outputs
right-shift and left-shift serial inputs operating-mode-control
inputs and a direct overriding clear line The register has
four distinct modes of operation namely
Parallel (broadside) load
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs S0
and S1 high The data is loaded into the associated flip-
flops and appears at the outputs after the positive transition
of the clock input During loading serial data flow is inhibit-
ed
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is high and S1 is low
Serial data for this mode is entered at the shift-right data
input When S0 is low and S1 is high data shifts left syn-
chronously and new data is entered at the shift-left serial
input
Clocking of the flip-flop is inhibited when both mode control
inputs are low The mode controls of the DM54194
DM74194 should be changed only while the clock input is
high
Features
Y
Y
Y
Y
Y
Y
Parallel inputs and outputs
Four operating modes
Synchronous parallel load
Right shift
Left shift
Do nothing
Positive edge-triggered clocking
Direct overriding clear
Typical clock frequency 36 MHz
Typical power dissipation 195 mW
Connection Diagram
Dual-In-Line Package
TL F 6564 鈥?1
Order Number DM54194J or DM54194W
See NS Package Number J16A or W16A
C
1995 National Semiconductor Corporation
TL F 6564
RRD-B30M105 Printed in U S A
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