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DM4M32SJ-12L Datasheet

  • DM4M32SJ-12L

  • Enhanced DRAM (EDRAM) Module

  • 24頁

  • ETC

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Enhanced
Features
s
Memory Systems Inc.
DM4M32SJ
4Mb x 32 Enhanced DRAM SIMM
Product Specification
Architecture
The DM4M32SJ achieves
4Mb x 32 density by mounting
32 4M x 1 EDRAMs, packaged
in 28-pin plastic SOJ packages
on both sides of the multi-
layer substrate. Four buffers
have been added to reduce the
loading on the address and
control lines. The buffers have
balanced output current levels
and current limiting resistors.
These offer low ground
Description
bounce, minimal undershoot,
and controlled fall times.
The Enhanced Memory Systems 16MB EDRAM SIMM module
The EDRAM memory
provides a single memory module solution for the main memory or
module architecture is very
local memory of fast PCs, workstations, servers, and other high
similar to a standard 16MB DRAM module with the addition of an
performance systems. Due to its fast 12ns cache row register, the
integrated cache and on-chip control which allows it to operate much
EDRAM memory module supports zero-wait-state burst read
operations at up to 66MHz bus rates in a non-interleave configuration like a page mode or static column DRAM.
The EDRAM's SRAM cache is integrated into the DRAM array as
and >100MHz bus rates with a two-way interleave configuration.
tightly coupled row registers. Memory reads always occur from the
On-chip write posting and fast page mode operation supports
cache row register. When the on-chip comparator detects a page hit,
12ns write and burst write operations. On a cache miss, the fast
DRAM array reloads the entire 8Kbyte cache over an 8Kbyte-wide bus only the SRAM is accessed and data is available in 12ns from column
in 18ns for an effective bandwidth of 454 Gbytes/sec. This means very address. When a page read miss is detected, the entire new DRAM row
is updated into the cache and data is available at the output all within
low latency and fewer wait states on a cache miss than a non-
a single 30ns access. Subsequent reads within the page (burst reads,
integrated cache/DRAM solution. The JEDEC compatible SIMM
local instructions, or data) will continue at 12ns cycle time. Since reads
configuration allows a single memory controller to be designed to
support either JEDEC slow DRAMs or high speed EDRAMs to provide occur from the SRAM cache, DRAM precharge can occur simultaneously
without degrading performance. The on-chip refresh counter with
a simple upgrade path to higher system performance.
independent refresh bus allows the EDRAM to
be refreshed during cache reads.
DM4M32SJ Functional Diagram
Memory writes are internally posted in
12ns and directed to the DRAM array. During
A
0-10
Column
CAL
0-3
Add
Column Decoder
a write hit, the on-chip address comparator
Latch
activates a parallel write path to the SRAM
2048 X 32 Cache (Row Register)
11-Bit
cache to maintain coherency. The EDRAM
Comp
Sense Amps
delivers 12ns cycle page mode memory writes.
G
& Column Write Select
I/O
Last
Memory writes do not affect the contents of
Control
Row
DQ
0-31
and
Read
A
0-10
the cache row register except during a cache
Data
Add
Latches
Latch
hit.
S
By integrating the SRAM cache as row
Memory
Row
Array
WE
Add
registers in the DRAM array and keeping the
16Mbyte
Latch
on-chip control simple, the EDRAM is able to
provide superior performance over standard
V
slow DRAMs.
A
0-9
C
Integrated 2,048 x 32 SRAM Cache Row Register Allows 12ns
Access Random Reads Within the Page
s
Interleaved SRAM Cache for 8ns Burst Reads
s
30ns DRAM Array for Fast Random Access to Any Page
s
Ultra-Fast Integrated 8Kbyte-Wide DRAM to Cache Bus
for 454-Gbyte/sec Cache Fill Bandwidth
s
On-Chip Write Posting and Fast Page Mode Operation Allows
12ns Writes and Burst Writes
s
On-Board Address and Control Buffering
s
Low Power Self Refresh Mode Option
Row Decoder
CC
F
W/R
RE
0,2
Row Add
and
Refresh
Control
1-36
Refresh
Counter
V
SS
PD
PD16M
The information contained herein is subject to change without notice. Enhanced reserves the right
to change or discontinue this product without notice.
漏 1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
38-2110-002

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