CD74HC259,
CD74HCT259
Data sheet acquired from Harris Semiconductor
SCHS173
November 1997
High Speed CMOS Logic
8-Bit Addressable Latch
Description
The Harris CD74HC259 and CD74HCT259 Addressable
Latch features the low-power consumption associated with
CMOS circuitry and has speeds comparable to low-power
Schottky.
This latches three active modes and one reset mode. When
both the Latch Enable (LE) and Master Reset (MR) inputs are
low (8-line Demultiplexer mode) the output of the addressed
latch follows the Data input and all other outputs are forced
low. When both MR and LE are high (Memory Mode), all
outputs are isolated from the Data input, i.e., all latches hold
the last data presented before the LE transition from low to
high. A condition of LE low and MR high (Addressable Latch
mode) allows the addressed latch鈥檚 output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when LE is high and MR is low.
Features
鈥?Buffered Inputs and Outputs
鈥?Four Operating Modes
鈥?Typical Propagation Delay of 15ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
[ /Title
(CD74
HC259
,
CD74
HCT25
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)
Ordering Information
PART NUMBER
CD74HC259E
CD74HCT259E
CD74HC259M
CD74HCT259M
NOTES:
1. When ordering, use the entire part number. Add the suf鏗亁 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
PKG.
NO.
E16.3
E16.3
M16.15
M16.15
Pinout
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 V
CC
15 MR
14 LE
13 D
12 Q7
11 Q6
10 Q5
9 Q4
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
Harris Corporation 1997
File Number
1727.1
1
1
2
3
4
5
6
7
8
9
