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DAC5674 Datasheet

  • DAC5674

  • 14BIT 400 MSPS, 2 X/ 4X INTERPOLATING COMMS DAC DIGITAL TO A...

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DAC5674
SLWS148 鈭?SEPTEMBER 2003
14 BIT, 400 MSPS, 2x/4x INTERPOLATING CommsDAC錚?/div>
DIGITAL TO ANALOG CONVERTER
FEATURES
D
200-MSPS Maximum Input Data Rate
D
400-MSPS Maximum Update Rate DAC
D
76-dBc SFDR Over Full First Nyquist Zone
With Single Tone Input Signal (F
out
= 21 MHz)
D
Differential Scalable Current Outputs: 2 mA to
20 mA
D
On-Chip 1.2-V Reference
D
1.8-V Digital and 3.3-V Analog Supply
D
D
D
Operation
1.8/3.3-V CMOS Compatible Interface
Power Dissipation: 435 mW at 400 MSPS
Package: 48-Pin TQFP
D
74-dBc ACPR W-CDMA at 15.36 MHz IF
D
69-dBc ACPR W-CDMA at 30.72 MHz IF
D
Selectable 2x or 4x Interpolation Filter
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
Linear Phase
0.05-dB Passband Ripple
80-dB Stopband Attenuation
Stopband Transition 0.4鈭?.6 F
data
nterpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For
Selection Higher Order Image
APPLICATIONS
D
Cellular Base Transceiver Station Transmit
Channel
鈭?CDMA: W鈭扖DMA, CDMA2000, IS鈭?5
鈭?TDMA: GSM, IS鈭?36, EDGE/UWC鈭?36
Test and Measurement: Arbitrary Waveform
Generation
Direct Digital Synthesis (DDS)
Cable Modem Termination System
D
D
D
D
On-chip 2x/4x PLL Clock Multiplier, PLL
Bypass Mode
DESCRIPTION
The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated
4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.
The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.
In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated

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