PLL52C63-01
Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers
FEATURES
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Generates all clock frequencies for Pentium (II), AMD
and Cyrix system requiring multiple CPU clocks.
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Supports up to16 Synchronous CPU clocks (4 CPU and
12 SDRAM) and 7 Synchronous PCI BUS clocks.
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Two 14.318Mhz reference clocks and one 2.5V IOAPIC
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One 24Mhz floppy clock and one 48Mhz USB clock.
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Power management control pins to stop CPU, SDRAM
or PCI BUS clocks.
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Supports 2-wire I2C serial bus interface.
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50% duty cycle with low jitter
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Mixed voltage support from 3.0 to 5V or (VDDq2=2.5V)
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Available in 300mil 48 pin SSOP.
PIN INFORMATION
FREQUENCY SELECTION (MHz)
F2
0
0
0
0
1
1
1
1
F1
0
0
1
1
0
0
1
1
F0 PCLK/SDRAM
0
1
0
1
0
1
0
1
50
100
83.3
68.5
55
75
60
66.6
BCLK
25
50
41.6
34.2
27.5
37.5
30
33.3
Note
: F2,F1,F0 and MODE are se lecta ble only dur ing power- on. They are
HIGH by de fault and LOW when 10K
鈩?/div>
Pull down is at tached.
I/O MODE CONFIGURATION
MODE
1 (OUT PUT)
0 (IN PUT)
PIN15
BCLK5
PCISTP
PIN46
REF1
CPUSTP
BLOCK DIAGRAM
45437 Warm Springs Blvd., Fre mont, Cali for nia 94539, TEL 510- 492- 0990 FAX 510- 492- 0991
9704.Rev.1C Page 1
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