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CYW2331 Datasheet

  • CYW2331

  • Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers

  • 12頁(yè)

  • CYPRESS

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1CYW2331
PRELIMINARY
CYW2331
Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers
Features
鈥?Operating voltage: 2.7V to 5.5V
鈥?PLL1 operating frequency:
鈥?2.0 GHz with prescaler ratios of 64/65 and 128/129
鈥?PLL2 operating frequency:
鈥?600 MHz with prescaler ratios of 8/9 and 16/17
鈥?Lock detect feature
鈥?Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
鈥?Available in a 24-pin CSP (Chip Scale Package)
鈥?Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2331 is a dual serial input PLL frequency
synthesizer which includes a 2.0-GHz RF and a 600-MHz IF
dual modulus prescaler to combine the RF and IF mixer fre-
quency sections of wireless communication systems. The syn-
thesizer is designed for cordless/cellular telephone systems,
cable TV tuners, WLANs and other wireless communication
systems. The device operates from 2.7V and dissipates only
24 mW.
CYW2331 Dual Hi-Lo PLL Block Diagram
GND (4)
GND (7)
V
CC
1 (1)
V
CC
2 (20)
V
P
1 (2)
F
IN
1 (5)
F
IN
1# (6)
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
fp1
Phase
Detector
Charge
Pump
D
O
PLL1 (3)
19-Bit
Latch
OSC_IN (8)
Pwr-dwn
PLL1
fr1
fr fp
Monitor
Output
Selector
15-Bit
Reference Counter
Latch
Selector
LE (13)
DATA (12)
CLOCK (11)
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
19-Bit
Latch
Pwr-dwn
PLL2
F
O
/LD (10)
fr2
Cntrl 22-Bit
Shift
Reg.
Power
Control
F
IN
2 (16)
F
IN
2# (15)
Prescaler
8/9 or
16/17
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Phase
Detector
fp2
Charge
Pump
D
O
PLL2 (18)
GND (14)
GND (9)
GND (17)
V
P
2 (19)
Pin Configuration
Vcc1
Vcc2
Vp1
24
23
18
17
D
O
PLL1
GND
F
IN
1
F
IN
1#
GND
OSC_IN
GND
F
O
/LD
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
D
O
PLL2
GND
F
IN
2
F
IN
2#
GND
LE
DATA
CLOCK
DoPLL1
GND
Fin1
Fin1#
GND
OSC_IN
NC
3
4
5
6
7
8
10
11
12
9
19
18
GND
Fin2
Fin2#
GND
LE
DATA
NC
DoPLL1
GND
Fin1
Fin1#
GND
16
Vp1
2
19
DoPLL2
1
2
3
4
5
20
V
P
1
2
19
V
P
2
22
NC
1
21
20
NC
Vp2
V
CC
1
1
20
V
CC
2
DoPLL2
Vp2
Vcc1
Vcc2
15
14
GND
Fin2
Fin2#
GND
LE
(Top View)
17
16
15
14
13
(Top View)
13
12
11
Fo/LD
CLOCK
OSC_IN
TSSOP
CSP
MLF
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
February 12, 2001. Rev. **
CLOCK
Fo/LD
DATA
GND
GND
10
6
7
8
9

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