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CYV15G0404DXB_07 Datasheet

  • CYV15G0404DXB_07

  • Independent Clock Quad HOTLink II⑩ Transceiver with Reclock...

  • 44頁

  • CYPRESS

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CYV15G0404DXB
Independent Clock Quad HOTLink II鈩?/div>
Transceiver with Reclocker
Features
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Synchronous LVTTL parallel interface
JTAG boundary scan
Built In Self Test (BIST) for at-speed link testing
Link quality indicator by channel
鉂?/div>
Analog signal detect
鉂?/div>
Digital signal detect
Low power 3W at 3.3V typical
Single 3.3V supply
256 ball thermally enhanced BGA
0.25渭 BiCMOS technology
JTAG device ID 鈥?C811069鈥檟
Quad channel transceiver for 195 to 1500 MBaud serial
signaling rate
鉂?/div>
Aggregate throughput of up to 12 Gbits/second
Second-generation
HOTLink
廬
technology
Compliant to multiple standards
鉂?/div>
SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre Channel, ES-
CON, and Gigabit Ethernet (IEEE802.3z)
鉂?/div>
10 bit uncoded data or 8B/10B coded data
Truly independent channels
鉂?/div>
Each channel is able to:
鈥?Perform reclocker function
鈥?Operate at a different signaling rate
鈥?Transport a different data format
Internal phase-locked loops (PLLs) with no external PLL
components
Selectable differential PECL compatible serial inputs per
channel
鉂?/div>
Internal DC restoration
Redundant differential PECL compatible serial outputs per
channel
鉂?/div>
No external bias resistors required
鉂?/div>
Signaling rate controlled edge rates
鉂?/div>
Source matched for 50惟 transmission lines
MultiFrame鈩?Receive Framer provides alignment options
鉂?/div>
Comma or full K28.5 detect
鉂?/div>
Single or multibyte Framer for byte alignment
鉂?/div>
Low latency option
Selectable input and output clocking options
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Functional Description
The CYV15G0404DXB Independent Clock Quad HOTLink II鈩?/div>
Transceiver is a point-to-point or point-to-multipoint communica-
tions building block enabling the transfer of data over a variety of
high speed serial links including SMPTE 292, SMPTE 259, and
DVB-ASI video applications. The signaling rate can be anywhere
in the range of 195 to 1500 MBaud for each serial link. Each
channel operates independently with its own reference clock
allowing different rates. Each transmit channel accepts parallel
characters in an input register, encodes each character for
transport, and then converts it to serial data. Each receive
channel accepts serial data and converts it to parallel data,
decodes the data into characters, and presents these characters
to an output register. The received serial data can also be
reclocked and retransmitted through the serial outputs.
Figure 1
illustrates typical connections between independent video
coprocessors and corresponding CYV15G0404DXB chips.
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Figure 1. HOTLink II鈩?System Connections
10
10
10
10
10
10
10
10
10
10
10
Cable
Connections
Serial Links
10
Independent
Channel
CYV15G0404DXB
Reclocker
Serial Links
Serial Links
10
Independent
Channel
CYV15G0404DXB
Reclocker
10
10
10
Serial Links
Cypress Semiconductor Corporation
Document #: 38-02097 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised December 14, 2007
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Video Coprocessor
Video Coprocessor

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