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CYV15G0101DXB Datasheet

  • CYV15G0101DXB

  • Single-channel HOTLink Transceiver

  • 39頁

  • CYPRESS

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CYP15G0101DXB
CYV15G0101DXB
Single-channel HOTLink II鈩?Transceiver
Features
鈥?Single-channel transceiver for 195 to 1500 MBaud serial
signaling rate
鈥?Second-generation HOTLink
廬
technology
鈥?Compliant to multiple standards
鈥?ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
鈥?CYV15G0101DXB also compliant to SMPTE 259M
and SMPTE 292M
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?8B/10B encoded or 10-bit unencoded data
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame鈩?Receive Framer
鈥?Bit and Byte alignment
鈥?Comma or full K28.5 detect
鈥?Single- or Multi-Byte framer for byte alignment
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Low-latency option
Synchronous LVTTL parallel input and parallel output
interface
Internal phase-locked loops (PLLs) with no external
PLL components
Dual differential PECL-compatible serial inputs
鈥?Internal DC-restoration
Dual differential PECL-compatible serial outputs
鈥?/div>
Source matched for driving 50W transmission lines
鈥?No external bias resistors required
鈥?Signaling-rate controlled edge-rates
鈥?Optional Elasticity Buffer in Receive Path
鈥?Optional Phase Align Buffer in Transmit Path
CYP(V)15G0101DXB
鈥?Compatible with
鈥?fiber-optic modules
鈥?copper cables
鈥?circuit board traces
鈥?JTAG boundary scan
鈥?Built-In Self-Test (BIST) for at-speed link testing
鈥?Per-channel Link Quality Indicator
鈥?Analog signal detect
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Digital signal detect
Low power 1.25W @ 3.3V typical
Single 3.3V supply
100-ball BGA
0.25m BiCMOS technology
Functional Description
The CYP(V)15G0101DXB
[1]
single-channel HOTLink II鈩?/div>
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. The receive channel accepts serial data and
converts it to parallel data, frames the data to character bound-
aries, decodes the framed characters into data and special
characters, and presents these characters to an Output
Register.
Figure 1
illustrates typical connections between
independent
host
systems
and
corresponding
CYP(V)15G0101DXB parts. As a second-generation HOTLink
device, the CYP(V)15G0101DXB extends the HOTLink II
family with enhanced levels of integration and faster data
rates, while maintaining serial-link compatibility (data,
command, and BIST) with other HOTLink devices.
CYP(V)15G0101DXB
System Host
10
10
10
10
Serial Link
Backplane or Cabled
Connections
Figure 1. HOTLink II System Connections
Note:
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices.
CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements.
CYP(V)15G0101DXB refers to both devices.
Cypress Semiconductor Corporation
Document #: 38-02031 Rev. *I
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised March 16, 2004
System Host

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