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CYK256K16MCCB Datasheet

  • CYK256K16MCCB

  • 4-Mbit (256K x 16) Pseudo Static RAM

  • 387.45KB

  • 10頁

  • CYPRESS

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CYK256K16MCCB
MoBL3鈩?/div>
4-Mbit (256K x 16) Pseudo Static RAM
Features
鈥?Wide voltage range: 2.70V鈥?.30V
鈥?Access time: 55 ns, 60 ns and 70 ns
鈥?Ultra-low active power
鈥?Typical active current: 1 mA @ f = 1 MHz
鈥?Typical active current: 8 mA @ f = f
max
(70-ns speed)
鈥?Ultra low standby power
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?Offered in a 48-ball BGA package
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/O
7
) is written into the location specified on the address pins
(A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE LOW) and Output Enable (OE) LOW while forcing
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. Refer to the truth table for a complete description of read
and write modes.
Functional Description
[1]
The CYK256K16MCCB is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life鈩?(MoBL
廬
) in
portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K 脳 16
RAM Array
SENSE AMPS
I/O0 鈥?I/O7
I/O8 鈥?I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Power- Down
Circuit
A
11
A
12
A
13
A
14
A
15
A
16
A
17
BHE
BLE
CE
Note:
1. For best practice recommendations, please refer to the CY application note
System Design Guidelines
on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05585 Rev. *F
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised October 18, 2006
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