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CYD18S72V-100BBC Datasheet

  • CYD18S72V-100BBC

  • FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM

  • 470.39KB

  • 26頁

  • CYPRESS

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PRELIMINARY
CYD04S72V
CYD09S72V
CYD18S72V
FLEx72鈩?3.3V 64K/128K/256K x 72
Synchronous Dual-Port RAM
Features
鈥?True dual-ported memory cells that allow simultaneous
access of the same memory location
鈥?Synchronous pipelined operation
鈥?Family of 4-Mbit, 9-Mbit and 18-Mbit devices
鈥?Pipelined output mode allows fast operation
鈥?0.18-micron CMOS for optimum speed and power
鈥?High-speed clock to data access
鈥?3.3V low power
鈥?Active as low as 225 mA (typ)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Standby as low as 55 mA (typ)
Mailbox function for message passing
Global master reset
Separate byte enables on both ports
Commercial and industrial temperature ranges
IEEE 1149.1-compatible JTAG boundary scan
484-ball FBGA (1 mm pitch)
Counter wrap around control
鈥?Internal mask register controls counter wrap-around
鈥?Counter-interrupt flags to indicate wrap-around
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Memory block retransmit operation
Counter readback on address lines
Mask register readback on address lines
Dual Chip Enables on both ports for easy depth
expansion
Seamless Migration to Next Generation Dual Port
Family
Functional Description
The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit
pipelined, synchronous, true dual-port static RAMs that are
high-speed, low-power 3.3V CMOS. Two ports are provided,
permitting independent, simultaneous access to any location
in memory. The result of writing to the same location by more
than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal set-up and
hold time.
During a Read operation, data is registered for decreased
cycle time. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle with chip enables asserted is required
to reactivate the outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap-around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CYD18S72V device have limited features. Please see
鈥淎ddress Counter and Mask Register Operations
[16]
鈥?on
page 6 for details.
Seamless Migration to Next Generation Dual Port Family
Cypress offers a migration path for all devices to the
next-generation devices in the Dual-Port family with a
compatible footprint. Please contact Cypress Sales for more
details
Table 1. Product Selection Guide
Density
Part Number
Max. Speed (MHz)
Max. Access Time - clock to Data (ns)
Typical operating current (mA)
Package
4-Mbit
(64K x 72)
CYD04S72V
167
4.0
225
484-ball FBGA
23mm x 23mm
9-Mbit
(128K x 72)
CYD09S72V
167
4.0
270
484-ball FBGA
23mm x 23mm
18-Mbit
(256K x 72)
CYD18S72V
133
5.0
410
484-ball FBGA
23mm x 23mm
Cypress Semiconductor Corporation
Document #: 38-06069 Rev. *D
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 23, 2004

CYD18S72V-100BBC 產(chǎn)品屬性

  • CYDxxS72V

  • 60

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，同步

  • 18M（256K x 72）

  • 100MHz

  • 并聯(lián)

  • 3.135 V ~ 3.465 V

  • 0°C ~ 70°C

  • 484-BGA

  • 484-FBGA（23x23）

  • 托盤

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