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CY8C29566-24AXIT Datasheet

  • CY8C29566-24AXIT

  • Mixed Signal Array

  • 40頁(yè)

  • CYPRESS

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PSoC鈩?Mixed Signal Array
CY8C29466, CY8C29566,
CY8C29666, and CY8C29866
Preliminary Data Sheet
Features
鈻?/div>
Powerful Harvard Architecture Processor
鉂?/div>
M8C Processor Speeds to 24 MHz
鉂?/div>
Two 8x8 Multiply, 32-Bit Accumulate
鉂?/div>
Low Power at High Speed
鉂?/div>
3.0V to 5.25V Operating Voltage
鉂?/div>
Operating Voltages Down to 1.0V Using On-
Chip Switch Mode Pump (SMP)
鉂?/div>
Industrial Temperature Range: -40擄C to +85擄C
鈻?/div>
Advanced Peripherals (PSoC Blocks)
鉂?/div>
12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs
- Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators
鉂?/div>
16 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Up to 4 Full-Duplex UARTs
- Multiple SPI鈩?Masters or Slaves
- Connectable to all GPIO Pins
鉂?/div>
Complex Peripherals by Combining Blocks
鈻?/div>
Precision, Programmable Clocking
鉂?/div>
Internal 鹵2.5% 24/48 MHz Oscillator
鉂?/div>
24/48 MHz with Optional 32.768 kHz Crystal
鉂?/div>
Optional External Oscillator, up to 24 MHz
鉂?/div>
Internal Oscillator for Watchdog and Sleep
鈻?/div>
Flexible On-Chip Memory
鉂?/div>
32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
鉂?/div>
2K Bytes SRAM Data Storage
鉂?/div>
In-System Serial Programming (ISSP鈩?
鉂?/div>
Partial Flash Updates
鉂?/div>
Flexible Protection Modes
鉂?/div>
EEPROM Emulation in Flash
鈻?/div>
Programmable Pin Configurations
鉂?/div>
25 mA Sink on all GPIO
鉂?/div>
Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO
鉂?/div>
Up to 12 Analog Inputs on GPIO
鉂?/div>
Four 40 mA Analog Outputs on GPIO
鉂?/div>
Configurable Interrupt on all GPIO
鈻?/div>
Additional System Resources
鉂?/div>
I
2
C鈩?Slave, Master, and Multi-Master to
400 kHz
鉂?/div>
Watchdog and Sleep Timers
鉂?/div>
User-Configurable Low Voltage Detection
鉂?/div>
Integrated Supervisory Circuit
鉂?/div>
On-Chip Precision Voltage Reference
鈻?/div>
Complete Development Tools
鉂?/div>
Free Development Software
(PSoC鈩?Designer)
鉂?/div>
Full-Featured, In-Circuit Emulator and
Programmer
鉂?/div>
Full Speed Emulation
鉂?/div>
Complex Breakpoint Structure
鉂?/div>
128K Bytes Trace Memory
鉂?/div>
Complex Events
鉂?/div>
C Compilers, Assembler, and Linker
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
PSoC鈩?Functional Overview
The PSoC鈩?family consists of many
Mixed Signal Array with
On-Chip Controller
devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
as well as programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of conve-
nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C29x66 family can have up to eight IO
ports that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Interrupt
Controller
Global Analog Interconnect
Flash 32K
SROM
PSoC CORE
Sleep and
Watchdog
CPU Core (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
(4 Rows,
16 Blocks)
ANALOG SYSTEM
Analog
Block
Array
(4 Columns,
12 Blocks)
Analog
Ref
Analog
Input
Muxing
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-
ture set. The core includes a CPU, memory, clocks, and config-
urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU utilizes an interrupt controller with 25 vec-
Digital
Clocks
Two
Multiply
Accum.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
August 3, 2004
漏 Cypress MicroSystems, Inc. 2004 鈥?Document No. 38-12013 Rev. *F
1

CY8C29566-24AXIT 產(chǎn)品屬性

  • CY8C29y66-24yXI(T)

  • Intro to PSoC

  • 1,500

  • 集成電路 (IC)

  • 嵌入式 - 微控制器，

  • PSOC®1 CY8C29xxx

  • M8C

  • 8-位

  • 24MHz

  • I²C，SPI，UART/USART

  • POR，PWM，WDT

  • 40

  • 32KB（32K x 8）

  • 閃存

  • -

  • 2K x 8

  • 3 V ~ 5.25 V

  • A/D 4x14b; D/A 4x9b

  • 內(nèi)部

  • -40°C ~ 85°C

  • 44-LQFP

  • 帶卷 (TR)

  • 428-2961-ND - KIT DEV FOR PSOC3/5428-2000-ND - EVALUATION POD FOR CY8C29X66428-1926-ND - KIT REF DESIGN LIN BUS428-1903-ND - PSOC POD FOR CY8C29428-1899-ND - PSOC POD FEET FOR 44-TQFP428-1889-ND - PSOC POD FEET FOR 28-DIP428-1885-ND - KIT ICE POD FOR CY8C29 DIP428-1880-ND - PSOC POD FOR CY8C29 QFN428-1585-ND - BOARD DEMO MINIPROG1428-1583-ND - KIT DEVELOPMENT FOR PSOC

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