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CY8C20160 Datasheet

  • CY8C20160

  • CapSense Express ⑩-6 Configurable IOs

  • 12頁

  • CYPRESS

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CY8C20160
CapSense Express
鈩?6 Configurable IOs
Features
鈻?/div>
Overview
The CapSense Express
TM
controller allows the control of 6 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I
2
C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
6 configurable IOs supporting
鉂?/div>
CapSense buttons
鉂?/div>
LED drive
鉂?/div>
Interrupt outputs
鉂?/div>
WAKE on interrupt input
鉂?/div>
User defined input or output
2.4V to 5.25V operating voltage
Industrial temperature range: 鈥?0擄C to +85擄C
I
2
C slave interface for configuration
鉂?/div>
Selectable to 50 kHz,100 kHz and 400 kHz.
Reduce BOM cost
鉂?/div>
Internal oscillator - no external oscillators or crystal
鉂?/div>
Free development tool - no external tuning components
Low operating current
鉂?/div>
Active current: continuous sensor scan:1.5 mA
鉂?/div>
Sleep current: no scan, continuous sleep:2.6 uA
Available in 16-pin COL and 16-pin SOIC packages
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Architecture
The logic block diagram shows the internal architecture of
CY8C20160.
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C20160 supports a standard I虜C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
鈻?/div>
鈻?/div>
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers. System
resources provide additional capability, such as a configurable
I
2
C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC block
which supports capacitive sensing of up to six inputs.
Cypress Semiconductor Corporation
Document Number:001-17347 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?408-943-2600
Revised March 11, 2008
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