鈥?/div>
Internal RAM, which is loaded from EEPROM
鈥?External memory device (128 pin package
鈥?Four programmable BULK/INTERRUPT/
ISOCHRONOUS endpoints
鈥?Buffering options: double, triple and quad
鈥?8- or 16-bit external data interface
鈥?GPIF
鈥?Allows direct connection to most parallel interface
鈥?Programmable waveform descriptors and configu-
ration registers to define waveforms
鈥?Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
鈥?/div>
Integrated, industry standard enhanced 8051:
鈥?Up to 48-MHz clock rate
鈥?Four clocks per instruction cycle
鈥?Two USARTS
鈥?Three counter/timers
鈥?Expanded interrupt system
鈥?Two data pointers
24-MHz
Ext. XTAL
High-performance micro
using standard tools
with lower-power options
Address (16)
鈥?Supports bus-powered applications by using renumer-
ation
鈥?3.3V operation
鈥?Smart Serial Interface Engine
鈥?Vectored USB interrupts
鈥?Separate data buffers for the SETUP and DATA portions
of a CONTROL transfer
鈥?Integrated I
2
C-compatible controller, runs at 100 or 400
kHz
鈥?48-MHz, 24-MHz, or 12-MHz 8051 operation
鈥?Four integrated FIFOs
鈥?Brings glue and FIFOs inside for lower system cost
鈥?Automatic conversion to and from 16-bit buses
鈥?Master or slave operation
鈥?FIFOs can use externally supplied clock or asyn-
chronous strobes
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?Easy interface to ASIC and DSP ICs
Special autovectors for FIFO and GPIF interrupts
Up to 40 general-purpose I/Os
Four package options鈥?28-pin TQFP, 100-pin TQFP,
56-pin QFN and 56-pin SSOP
Four packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP
Data (8)
FX2
Address (16) / Data Bus (8)
V
CC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Compatible
Master
Additional I/Os (24)
1.5k
connected for
full speed
D+
D鈥?/div>
Integrated
full- and high-speed
XCVR
USB
2.0
XCVR
CY
Smart
USB
1.1/2.0
Engine
8.5 kB
RAM
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
RDY (6)
CTL (6)
4 kB
FIFO
8/16
Up to 96 MBytes/s
burst rate
Enhanced USB core
Simplifies 8051 core
鈥淪oft Configuration鈥?/div>
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08012 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 8, 2005
next
CY7C68013相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Cypress
-
英文版
32K x 8/9 Dual-Port Static RAM
Cypress
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS
-
英文版
64K/128K x 8/9 Dual-Port Static RAM
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
CYPRESS [C...
-
英文版
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
Cypress
-
英文版
16K x 16/18 Dual-Port Static RAM
Cypress
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS
-
英文版
32K/64K x 16/18 Dual-Port Static RAM
CYPRESS [C...