CY7C68001-56PVC Datasheet

IC型號：
CY7C68001-56PVC
PDF描述：
EZ-USB SX2⑩ High-Speed USB Interface Device
文件大小：
985.41KB
PDF頁數(shù)：
43頁
芯片廠家：
CYPRESS

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CY7C68001

EZ-USB

SX2鈩?/div>

High-Speed USB Interface Device

1.0

EZ-USB

SX2鈩?/div>

Features

2.0

Applications

鈥?USB 2.0-certified compliant

鈥?On the USB-IF Integrators List: Test ID Number

40000713

鈥?Operates at high (480 Mbps) or full (12 Mbps) speed

鈥?Supports Control Endpoint 0:

鈥?Used for handling USB device requests

鈥?Supports four configurable endpoints that share a 4-

KB FIFO space

鈥?Endpoints 2, 4, 6, 8 for application-specific control

and data

鈥?Standard 8- or 16-bit external master interface

鈥?Glueless interface to most standard microproces-

sors DSPs, ASICs, and FPGAs

鈥?Synchronous or Asynchronous interface

鈥?Integrated phase-locked loop (PLL)

鈥?3.3V operation, 5V tolerant I/Os

鈥?56-pin SSOP and QFN package

鈥?Complies with most device class specifications

鈥?DSL modems

鈥?ATA interface

鈥?Memory card readers

鈥?Legacy conversion devices

鈥?Cameras

鈥?Scanners

鈥?Home PNA

鈥?Wireless LAN

鈥?MP3 players

鈥?Networking

鈥?Printers

The 鈥淩eference Designs鈥?section of the Cypress web site

provides additional tools for typical USB applications. Each

reference design comes complete with firmware source code

and object code, schematics, and documentation. Please see

the Cypress web site at www.cypress.com.

2.1

Block Diagram

SCL

I2C Bus

Controller

(Master Only)

SDA

WAKEUP*

RESET#

IFCLK*

24 MHz

XTAL

PLL

Read*, Write*, OE*, PKTEND*, CS#

Interrupt#, Ready

SX2 Internal Logic

Flags (3/4)

Address (3)

Control

VCC

1.5K

FIFO

Data

Bus

USB 2.0 XCVR

CY Smart USB

FS/HS Engine

4 KB

FIFO

Data

8/16-Bit Data

DPLUS

DMINUS

Figure 2-1. Block Diagram

Cypress Semiconductor Corporation

Document #: 38-08013 Rev. *E

鈥?/div>

3901 North First Street

鈥?/div>

San Jose

鈥?/div>

CA 95134 鈥?/div>

408-943-2600

Revised July 13, 2004

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