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CY7C4282V_03 Datasheet

  • CY7C4282V_03

  • 64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and...

  • 214.56KB

  • 15頁

  • CYPRESS

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CY7C4282V
CY7C4292V
64K/128K x 9 Low-Voltage Deep Sync FIFOs
with Retransmit and Depth Expansion
Features
鈥?3.3V operation for low power consumption and easy
integration into low-voltage systems
鈥?High-speed, low-power, first-in first-out (FIFO)
memories
鈥?64K 脳 9 (CY7C4282V)
鈥?128K 脳 9 (CY7C4292V)
鈥?0.35 micron CMOS for optimum speed/power
鈥?High-speed, Near-Zero Latency (True Dual-Ported
Memory Cell), 100-MHz operation (10 ns read/write
cycle times)
鈥?Low power
鈥?/div>
I
CC
= 25 mA
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
I
SB
= 6 mA
Fully asynchronous and simultaneous read and write
operation
Empty, Full, and Programmable Almost Empty and
Almost Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability through token-passing
scheme (no external logic required)
64-pin 10 脳 10 STQFP
Pin-compatible 3.3V solution for CY7C4282/92
Functional Description
The CY7C4282V/92V are high-speed, low-power, FIFO
memories with clocked read and write interfaces. All devices
are nine bits wide. The CY7C4282V/92V can be cascaded to
increase FIFO depth. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, video and communica-
tions buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a Write
Enable pin (WEN).
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the Cascade Input (XI),
Cascade Output (XO), and First Load (FL) pins. The XO pin is
connected to the XI pin of the next device, and the XO pin of
the last device should be connected to the XI pin of the first
device. The FL pin of the first device is tied to VSS and the FL
pin of all the remaining devices should be tied to VCC
When WEN is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN is held active, data
is continually written into the FIFO on each cycle. The output
port is controlled in a similar manner by a free-running Read
Clock (RCLK) and a Read Enable pin (REN). In addition, the
CY7C4282V/92V have an Output Enable pin (OE). The read
and write clocks may be tied together for single-clock
operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to
67 MHz are achievable.
Logic Block Diagram
D
0鈥?
INPUT
REGISTER
WCLK WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
FLAG
LOGIC
Dual Port
RAM Array
64K x 9
128K x 9
READ
POINTER
EF
PAE
PAF/XO
WRITE
POINTER
RS
RESET
LOGIC
FL/RT
XI/LD
PAF/XO
EXPANSION
LOGIC
THREE-STATE
OUTPUT REGISTER
Q
0
鈭?/div>
8
OE
READ
CONTROL
RCLK REN
Cypress Semiconductor Corporation
Document #: 38-06014 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised August 22, 2003

CY7C4282V_03相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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