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CY7C373 Datasheet

  • CY7C373

  • UltraLogic?64-Macrocell Flash CPLD

  • Cypress

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USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
CY7C373i
UltraLogic鈩?64-Macrocell Flash CPLD
Features
鈥?64 macrocells in four logic blocks
鈥?64 I/O pins
鈥?5 dedicated inputs including 4 clock pins
鈥?In-System Reprogrammable鈩?(ISR鈩? Flash
technology
鈥?JTAG interface
鈥?Bus Hold capabilities on all I/Os and dedicated inputs
鈥?No hidden delays
鈥?High speed
鈥?f
MAX
= 125 MHz
鈥?t
PD
= 10 ns
鈥?t
S
= 5.5 ns
鈥?t
CO
= 6.5 ns
鈥?Fully PCI compliant
鈥?3.3V or 5.0V I/O operation
鈥?Available in 84-pin PLCC and 100-pin TQFP packages
鈥?Pin compatible with the CY7C374i
Functional Description
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i鈩?family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C373i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic鈩?F
LASH
370i devices, the CY7C373i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
CLOCK
INPUTS
Logic Block Diagram
INPUT
1
INPUT
MACROCELL
2
16 I/Os
I/O
0
-I/O
15
LOGIC
BLOCK
A
4
INPUT/CLOCK
MACROCELLS
2
16 I/Os
I/O
48
鈭捍/O
63
36
16
PIM
36
16
LOGIC
BLOCK
D
16 I/Os
I/O
16
-I/O
31
LOGIC
BLOCK
B
36
16
36
16
LOGIC
BLOCK
C
16 I/Os
I/O
32
鈭捍/O
47
32
32
Selection Guide
7C373i鈥?25 7C373i鈥?00
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
10
5.5
6.5
75
12
6.0
6.5
75
7C373i鈥?3
15
8
8
75
7C373iL-83
15
8
8
45
7C373i鈥?6
20
10
10
75
7C373iL鈥?6
20
10
10
45
Note:
1. The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
Cypress Semiconductor Corporation
Document #: 38-03030 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 8, 2004

CY7C373相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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