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CY7C372i Datasheet

  • CY7C372i

  • UltraLogic 64-Macrocell Flash CPLD

  • Cypress

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USE ULTRA37000鈩?/div>
FOR ALL NEW DESIGNS
CY7C372i
UltraLogic鈩?64-Macrocell Flash CPLD
Features
鈥?64 macrocells in four logic blocks
鈥?32 I/O pins
鈥?Five dedicated inputs including two clock pins
鈥?In-System Reprogrammable (ISR鈩? Flash technology
鈥?JTAG interface
鈥?Bus Hold capabilities on all I/Os and dedicated inputs
鈥?No hidden delays
鈥?High speed
鈥?f
MAX
= 125 MHz
鈥?t
PD
= 10 ns
鈥?t
S
= 5.5 ns
鈥?t
CO
= 6.5 ns
鈥?Fully PCI compliant
鈥?3.3V or 5.0V I/O operation
鈥?Available in 44-pin PLCC, TQFP, and CLCC packages
鈥?Pin-compatible with the CY7C371i
Functional Description
The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i鈩?family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C372i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic鈩?F
LASH
370i devices, the CY7C372i
is electrically erasable and ISR, which simplifies both design
and manufacturing flows, thereby reducing costs. The
Cypress ISR function is implemented through a JTAG serial
interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
voltage pin (ISR
EN
). Additionally, because of the superior
routability of the F
LASH
370i devices, ISR often allows users to
change existing logic designs while simultaneously fixing
pinout assignments.
The 64 macrocells in the CY7C372i are divided between four
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource鈥攖he
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Logic Block Diagram
INPUTS
CLOCK
INPUTS
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
BLOCK
D
8 I/Os
I/O
24
-I/O
31
3
INPUT
MACROCELLS
2
8 I/Os
I/O
0
-I/O
7
LOGIC
BLOCK
A
36
16
PIM
36
16
8 I/Os
I/O
8
-I/O
15
LOGIC
BLOCK
B
36
16
36
16
LOGIC
BLOCK
C
8 I/Os
I/O
16
-I/O
23
16
16
Cypress Semiconductor Corporation
Document #: 38-03033 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 16, 2004

CY7C372i相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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