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CY7C371-66AC Datasheet

  • CY7C371-66AC

  • UltraLogic 32-Macrocell Flash CPLD

  • 11頁

  • CYPRESS

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7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
UltraLogic
t
32 Macrocell Flash CPLD
Features
Functional Description
D
D
D
D
D
32 macrocells in two logic blocks
32 I/O pins
6 dedicated inputs including 2 clock
pins
No hidden delays
High speed
f
MAX
= 143 MHz
t
PD
= 8.5 ns
t
S
= 5 ns
t
CO
= 6 ns
The CY7C371 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the F
LASH
370 family of high den
sity, high speed CPLDs. Like all members
of the F
LASH
370 family, the CY7C371 is
designed to bring the ease of use and high
performance of the 22V10 to high density
CPLDs.
The 32 macrocells in the CY7C371 are di
vided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the F
LASH
370 architec
ture are connected with an extremely fast
and predictable routing resource the
Programmable
Interconnect
Matrix
(PIM). The PIM brings flexibility, rout
ability, speed, and a uniform delay to the
interconnect.
Like all members of the F
LASH
370 family,
the CY7C371 is rich in I/O resources.
Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very sim
ple timing model. Unlike other high den
sity CPLD architectures, there are no hid
den speed delays such as fanout effects, in
terconnect delays, or expander delays. Re
gardless of the number of resources used
or the type of application, the timing pa
rameters on the CY7C371 remain the
same.
D
D
D
Electrically alterable FLASH
technology
Available in 44 pin PLCC, CLCC, and
TQFP packages
Pin compatible with the CY7C372
Logic Block Diagram
INPUTS
CLOCK
INPUTS
4
INPUT
MACROCELLS
2
INPUT/CLOCK
MACROCELLS
2
2
PIM
16 I/Os
I/O
0
-I/O
15
LOGIC
BLOCK
A
16
16
36
36
LOGIC
BLOCK
B
16 I/Os
I/O
16
-I/O
31
16
16
7c371 1
Selection Guide
7C371-143
7C371-110
7C371-83
7C371L-83
7C371-66
7C371L-66
Maximum Propagation Delay, t
PD
(ns)
Minimum Set Up, t
S
(ns)
Maximum Clock to Output, t
CO
(ns)
Maximum Supply
Current,
Current I
CC
(mA)
Commercial
Military/Ind.
8.5
5
6
220
10
6
6.5
175
12
10
10
175
220
12
10
10
90
110
15
12
12
175
220
15
12
12
90
110
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
D
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
December 1993 - Revised August 1995

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