CY7C199C
256K (32K x 8) Static RAM
Features
鈥?Fast access time: 12 ns
鈥?Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
鈥?CMOS for optimum speed/power
鈥?TTL鈥揷ompatible Inputs and Outputs
鈥?2.0V Data Retention
鈥?Low CMOS standby power
鈥?Automated Power-down when deselected
鈥?Available in Pb-free and non Pb-free 28-pin (300-Mil)
Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I
packages
General Description
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
See the Truth Table in this data sheet for a complete
description of read and write modes
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
ARRAY
32K x 8
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
A
X
X
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current (L)
12
85
15 ns
15
80
500
20 ns
20
75
Unit
ns
mA
碌A(chǔ)
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised August 3, 2006
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