CY7C199C
32K x 8 Static RAM
Features
鈥?Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns
鈥?Wide voltage range: 5.0V 鹵 10% (4.5V to 5.5V)
鈥?CMOS for optimum speed/power
鈥?TTL鈥揷ompatible Inputs and Outputs
鈥?Available in 28 DIP, 28 SOJ, and 28 TSOP I.
鈥?2.0V Data Retention
鈥?Low CMOS standby power
鈥?Automated Power鈥揹own when deselected
General Description
1
The CY7C199C is a high鈥損erformance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power鈥揹own feature that significantly reduces
power consumption when deselected.
See the Truth Table in this datasheet for a complete
description of read and write modes.
The CY7C199C is available in 28 DIP, 28 SOJ, and 28 TSOP
I package(s).
Logic Block Diagram
Input Buffer
Row Decoder
RAM Array
Sense Amps
I/Ox
CE
Column Decoder
Power
Down
Circuit
WE
OE
A
X
X
Product Portfolio
12 ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
(low power)
12
85
500
15 ns
15
80
500
20 ns
20
75
500
25 ns
25
75
500
Unit
ns
mA
uA
Notes:
1. For best鈥損ractices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised September 11, 2003
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