CY7C192
64K x 4 Static RAM
with Separate I/O
Features
鈥?High speed
鈥?12 ns
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?860 mW
鈥?Low standby power
鈥?55 mW
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?Available in non Pb-free 28-Lead Molded SOJ package.
Functional Description
The CY7C192 is a high-performance CMOS static RAM
organized as 65,536 x 4 bits with separate I/O. Easy memory
expansion is provided by active LOW Chip Enable (CE) and
tri-state drivers. It has an automatic power-down feature,
reducing the power consumption by 75% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and write enable (WE) inputs are both LOW.
Data on the four input pins (I
0
through I
3
) is written into the
memory location specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW while the Write Enable (WE) remains HIGH. Under
these conditions the contents of the memory location specified
on the address pins will appear on the four data output pins.
The output pins stay in high-impedance state when Write
Enable (WE) is LOW, or Chip Enable (CE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
I
0
I
1
I
2
I
3
INPUT BUFFER
Pin Configurations
SOJ
Top View
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
I
0
I
1
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
I
3
I
2
O
3
O
2
O
1
O
0
WE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
ROW DECODER
O
0
SENSE AMPS
64K x 4
ARRAY
O
1
O
2
O
3
COLUMN
DECODER
POWER
DOWN
A
10
A
11
A
12
A
13
A
14
A
15
CE
WE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
-12
12
155
10
-15
15
145
10
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05047 Rev. *C
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised August 3, 2006
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