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CY7C186-35PC Datasheet

  • CY7C186-35PC

  • 8Kx8 Static RAM

  • 9頁(yè)

  • CYPRESS

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86
CY7C186
8Kx8 Static RAM
Features
鈥?High speed
鈥?20 ns
鈥?Low active power
鈥?605 mW
鈥?Low standby power
鈥?110 mW
鈥?CMOS for optimum speed/power
鈥?Easy memory expansion with CE
1
, CE
2
, and OE
features
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), and active LOW output enable (OE) and
three-state drivers. The device has an automatic power-down
feature (CE
1
), reducing the power consumption by over 80%
when deselected. The CY7C186 is in a 600-mil-wide PDIP
package and a 32-pin TSOP (std. pinout).
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Functional Description
The CY7C186 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
LogicBlock Diagram
Pin Configuration
DIP
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
POWER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
256 x 32 x 8
ARRAY
COLUMN DECODER
DOWN
I/O
7
10
A
A
A
A
Selection Guide
[1]
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Notes:
1. For military specifications, see the CY7C186A datasheet.
A
12
11
0
9
7C186-20
20
110
20/15
7C186-25
25
100
20/15
7C186-35
35
100
20/15
Cypress Semiconductor Corporation
Document #: 38-05280 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 22, 2002

CY7C186-35PC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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