CY7C182
8Kx9 Static RAM
Features
鈥?High speed
鈥?t
AA
= 25 ns
鈥?x9 organization is ideal for cache memory applications
鈥?CMOS for optimum speed/power
鈥?Low active power
鈥?770 mW
鈥?Low standby power
鈥?195 mW
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?Easy memory expansion with CE
1
, CE
2
, OE options
The CY7C182, which is oriented toward cache memory appli-
cations, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE
1
), an active HIGH Chip En-
able (CE
2
), an active-LOW Output Enable (OE), and three-
state drivers.
An active-LOW Write Enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
1
and WE in-
puts are both LOW, data on the nine data input/output pins
(I/O
0
through I/O
8
) is written into the memory location ad-
dressed by the address present on the address pins (A
0
through A
12
). Reading the device is accomplished by selecting
the device and enabling the outputs, (CE
1
and OE active LOW
and CE
2
active HIGH), while (WE) remains inactive or HIGH.
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress鈥檚 high-
performance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
0
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
CE
1
CE
2
WE
OE
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
I/O
3
GND
256 x 32 x 9
ARRAY
COLUMN
DECODER
A
10
A
11
A
12
A
0
A
9
POWER
DOWN
I/O
7
I/O
8
C182鈥?
C182鈥?
Selection Guide
7C182-25
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
25
140
35
7C182-35
35
140
35
7C182-45
45
140
35
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
October 4, 1999
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