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CY7C167A-15VC Datasheet

  • CY7C167A-15VC

  • 16K x 1 Static RAM

  • 9頁

  • CYPRESS

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67A
CY7C167A
16K x 1 Static RAM
Features
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?High speed
鈥?15 ns
鈥?Low active power
鈥?495 mW
鈥?Low standby power
鈥?220 mW
鈥?TTL-compatible inputs and outputs
鈥?Capable of withstanding greater than 2001V electro-
static discharge
鈥?V
IH
of 2.2V
Functional Description
The CY7C167A is a high-performance CMOS static RAM or-
ganized as 16,384 words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and three-state
drivers. The CY7C167A has an automatic power-down fea-
ture, reducing the power consumption by 67% when
deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A
0
through A
13
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while (WE) remains HIGH. Under these conditions,
the contents of the location specified on the address pins will
appear on the data output (DO) pin.
The output pin remains in a high-impedance state when Chip
Enable is HIGH, or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
DIP
Top View
DI
A
0
A
1
A
2
A
3
A
4
A
5
A
6
DO
WE
GND
CE
1
2
3
4
5
6
7
8
9
10
7C167A
20
19
18
17
16
15
14
13
12
11
INPUT BUFFER
V
CC
A
13
A
12
A
11
A
10
A
9
A
8
A
7
DI
CE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
ROW DECODER
SENSE AMP
128 x 128
ARRAY
DO
C167A-2
COLUMN
DECODER
POWER
DOWN
WE
A13
A10
A11
A12
A7
A8
A9
C167A-1
Selection Guide
7C167A-15
Maximum Access Time (ns)
Maximum Operating Current (mA)
15
90
7C167A-20
20
90
7C167A-25
25
90
7C167A-35
35
90
7C167A-45
45
90
Cypress Semiconductor Corporation
Document #: 38-05027 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 24, 2001

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