音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY7C1471V33-100AXC Datasheet

  • CY7C1471V33-100AXC

  • 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoB...

  • 29頁

  • CYPRESS

掃碼查看芯片數據手冊

上傳產品規(guī)格書

PDF預覽

PRELIMINARY
CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL鈩?Architecture
Features
鈥?No Bus Latency鈩?(NoBL鈩? architecture eliminates
dead cycles between write and read cycles.
鈥?Can support up to 133-MHz bus operations with zero
wait states
鈥?Data is transferred on every clock
鈥?Pin compatible and functionally equivalent to ZBT鈩?/div>
devices
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Registered inputs for flow-through operation
鈥?Byte Write capability
鈥?3.3V/2.5V I/O power supply
鈥?Fast clock-to-output times
鈥?6.5 ns (for 133-MHz device)
鈥?8.5 ns (for 100-MHz device)
鈥?Clock Enable (CEN) pin to enable clock and suspend
operation
鈥?Synchronous self-timed writes
鈥?Asynchronous Output Enable
鈥?Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V33 and
CY7C1473V33. 209-ball fBGA package for
CY7C1475V33.
鈥?Three chip enables for simple depth expansion.
鈥?Automatic Power-down feature available using ZZ
mode or CE deselect.
鈥?JTAG boundary scan for BGA and fBGA packages
鈥?Burst Capability鈥攍inear or interleaved burst order
鈥?Low standby power
Functional Description
[1]
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
X
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
6.5
335
150
100 MHz
8.5
305
150
Unit
ns
mA
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *E
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 5, 2004

CY7C1471V33-100AXC相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯系人：

聯系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經采納，將有感恩紅包奉上哦！