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CY7C1464V25 Datasheet

  • CY7C1464V25

  • Memory

  • 26頁

  • ETC

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PRELIMINARY
CY7C1460V25
CY7C1462V25
CY7C1464V25
1M x 36/2M x 18/512K x 72 Pipelined SRAM
with NoBL鈩?Architecture
Features
鈥?Zero Bus Latency錚? no dead cycles between write and
read cycles
鈥?Fast clock speed: 250, 200, and 167 MHz
鈥?Fast access time: 2.7, 3.0 and 3.5 ns
鈥?Internally synchronized registered outputs eliminate
the need to control OE
鈥?Single 2.5V 鹵5% power supply V
DD
鈥?Separate V
DDQ
for 2.5V or 1.8V I/O
鈥?Single WE (Read/Write) control pin
鈥?Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
鈥?Interleaved or linear four-word burst capability
鈥?Individual byte write (BWS
a
鈥揃WS
h
) control (may be tied
LOW)
鈥?CEN pin to enable clock and suspend operations
鈥?Three chip enables for simple depth expansion
鈥?JTAG boundary scan for BGA packaging version
鈥?Available in 119-ball bump BGA, 165-ball FBGA
package and 100-pin TQFP packages (CY7C1460V25
and CY7C1462V25). 209 FBGA package for
CY7C1464V25
Clock Enable (CEN), Byte Write Selects (BWS
a
, BWS
b
,
BWS
c
,BWS
d,
BWS
e
, BWS
f
, BWS
g
, BWS
h
), and read-write
control (WE). BWS
c
and BWS
d
apply to CY7C1460V25 and
CY7C1464V25 only.BWS
e
, BWS
f,
BWS
g
, and BWS
h
apply to
CY7C1464V25 only
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either read or write.
A Clock Enable (CEN) pin allows operation of the
CY7C1460V25,CY7C1462V25 and CY7C1464V25 to be
suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers
will hold their previous values.
There are three Chip Enable (CE
1
, CE
2
, CE
3
) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is low, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(read or write) will be completed. The data bus will be in high
impedance state two cycles after chip is deselected or a write
cycle is initiated.
The CY7C1460V25,CY7C1462V25 and CY7C1464V25 have
an on-chip two-bit burst counter. In the burst mode,
CY7C1460V25,CY7C1462V25 and CY7C1464V25 provide
four cycles of data for a single address presented to the
SRAM. The order of the burst sequence is defined by the
MODE input pin. The MODE pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load
a new external address (ADV/LD = LOW) or increment the
internal burst counter (ADV/LD = HIGH)
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
D
Data-In REG.
Q
OUTOUT
REGISTERS
and LOGIC
Functional Description
The CY7C1460V25,CY7C1462V25 and CY7C1464V25
SRAMs are designed to eliminate dead cycles when transi-
tions from READ to WRITE or vice versa. These SRAMs are
optimized for 100 percent bus utilization and achieves Zero
Bus Latency. They integrate 1,048,576 x 36/2,097,152 x 18/
524,288 x 72 SRAM cells, respectively, with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. The Synchronous Burst SRAM family
employs high-speed, low-power CMOS designs using
advanced single layer polysilicon, three-layer metal
technology. Each memory cell consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
, and CE
3
), cycle start input (ADV/LD),
Logic Block Diagram
CLK
CE
ADV/LD
A
x
1Mx36
2Mx18
CEN
CE
1
CE
2
DQ
X
A
X
BWS
X
CE
3
DP
X
WE
X = a, b
X = 19:0 X = a, b, X= a, b, , c, d
BWS
x
c, d
c, d
CONTROL
and WRITE
LOGIC
1Mx36
2Mx18
512Kx72
MEMORY
ARRAY
DQ
x
DP
x
Mode
X = 20:0 X = a, b X = a, b X = a, b
X = a, b, X = a, b
512Kx72
X = 18:0 X = a, b,
c,d,e,f,g,h c,d,e,f,g,h c,d,e,f,g,h
OE
Cypress Semiconductor Corporation
Document #: 38-05191 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose, CA 95134
鈥?/div>
408-943-2600
Revised November 14, 2002

CY7C1464V25相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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