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CY7C1399 Datasheet

  • CY7C1399

  • 32K x 8 3.3V Static RAM

  • Cypress

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CY7C1399
32K x 8 3.3V Static RAM
Features
鈥?Single 3.3V power supply
鈥?Ideal for low-voltage cache memory applications
鈥?High speed
鈥?12/15 ns
鈥?Low active power
鈥?255 mW (max.)
鈥?Low CMOS standby power (L)
鈥?/div>
180
碌W
(max.), f=f
MAX
鈥?2.0V data retention (L)
鈥?/div>
40
碌W
鈥?Low-power alpha immune 6T cell
鈥?Plastic SOJ and TSOP packaging
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the writing/
reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. The CY7C1399 is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Functional Description
The CY7C1399 is a high-performance 3.3V CMOS Static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
CE
WE
OE
ROW DECODER
I/O
2
SENSE AMPS
32K x 8
ARRAY
I/O
3
I/O
4
C1399鈥?
I/O
5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
A
14
C1399鈥?
Selection Guide
7C1399鈥?2
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (碌A(chǔ))
Maximum CMOS Standby Current (碌A(chǔ)) L
12
60
500
50
7C1399鈥?5
15
55
500
50
7C1399鈥?0
20
50
500
50
7C1399鈥?5
25
45
500
50
7C1399鈥?5
35
40
500
50
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
March 25, 1999

CY7C1399相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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