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CY7C1392V18 Datasheet

  • CY7C1392V18

  • Memory

  • 444.42KB

  • 24頁

  • ETC

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PRELIMINARY
CY7C1392V18
CY7C1393V18
CY7C1394V18
18-Mb DDR-II SIO SRAM Two-word
Burst Architecture
Features
鈥?18-Mb density (2M x 8, 1M x 18, 512K x 36)
鈥?Supports concurrent transactions
鈥?250-MHz clock for high bandwidth
鈥?Two-word burst for reducing address bus frequency
鈥?Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mismatches
鈥?Echo clocks (CQ and CQ) simplify data capture in high
speed systems
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?1.8V core power supply with HSTL inputs and outputs
鈥?Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?13x15 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15
matrix)
鈥?JTAG Interface
鈥?On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1392V18/CY7C1393V18/CY7C1394V18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR-II SIO
(Double Data Rate Separate I/O) architecture. The DDR-II SIO
consists of two separate DDR ports, Read and Write port, to
access the memory array. The Read port has dedicated
outputs and the Write port has dedicated inputs to support
read and write operations concurrently. Access to each port is
accomplished using a common address bus. Addresses for
Read and Write are latched on alternate rising edges of the
input (K) clock. Write data is registered on the rising edges of
both K and K. Read data is driven on the rising edges of C and
C if provided, or on the rising edge of K and K if C/C are not
provided. Each address location is associated with two 8-bit
words in the case of CY7C1392V18, two 18-bit words in the
case of CY7C1393V18, and two 36-bit words in the case of
CY7C1394V18, that burst sequentially into or out of the
device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C/C input clocks (or K/K in single
clock mode). Writes are conducted with on-chip synchronous
self-timed write circuitry.
Configuration
CY7C1392V18鈥?M x 8
CY7C1393V18鈥?M x18
CY7C1394V18鈥?12K x 36
Logic Block Diagram (CY7C1392V18)
D
[7:0]
8
Write
Data Reg
Write Add. Decode
Write
Data Reg
Read Add. Decode
A
(19:0)
20
Address
Register
K
K
1M x 8
Memory
Array
1M x 8
Memory
Array
CLK
Gen.
Control
Logic
Read Data Reg.
R/W
V
REF
LD
BWS
0
BWS
1
16
Control
Logic
8
Reg.
8
Reg.
8
LD
R/W
C
C
CQ
CQ
Reg. 8
8
Q
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05179 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised July 31, 2002

CY7C1392V18相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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