25/0251
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
Features
鈥?True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
鈥?4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
鈥?4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
鈥?0.35-micron CMOS for optimum speed/power
鈥?High-speed access: 20/25 ns
鈥?Low operating power
鈥?Active: I
CC
= 115 mA (typical)
鈥?Standby: I
SB3
= 10
碌A(chǔ)
(typical)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
鈥?On-chip arbitration logic
鈥?Semaphores included to permit software handshaking
between ports
鈥?INT flag for port-to-port communication
鈥?Pin select for Master or Slave
鈥?Commercial and Industrial Temperature Ranges
鈥?Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
鈥?Pin-compatible and functionally equivalent to
IDT70V05, 70V06, and 70V07.
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
[1]
8/9
8/9
[1]
I/O
0L
鈥揑/O
7/8L
I/O
Control
I/O
Control
I/O
0R
鈥揑/O
7/8R
[2]
12鈥?5
A
0L
鈥揂
11鈥?4L
Address
Decode
12鈥?5
True Dual-Ported
RAM Array
Address
Decode
12鈥?5
12鈥?5
[2]
A
0R
鈥揂
11鈥?4R
[2]
[2]
A
0L
鈥揂
11鈥?4L
CE
L
OE
L
R/W
L
SEM
L
[3]
Interrupt
Semaphore
Arbitration
A
0R
鈥揂
11鈥?4R
CE
R
OE
R
R/W
R
SEM
R
[3]
BUSY
L
INT
L
M/S
Notes:
1. I/O
0
鈥揑/O
7
for x8 devices; I/O
0
鈥揑/O
8
for x9 devices.
2. A
0
鈥揂
11
for 4K devices; A
0
鈥揂
12
for 8K devices; A
0
鈥揂
13
for 16K devices; A
0
鈥揂
14
for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
BUSY
R
INT
R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06051 Rev. *A
Revised December 27, 2002