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CY7C1387B Datasheet

  • CY7C1387B

  • Memory

  • 30頁

  • ETC

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1CY7C1386B
PRELIMINARY
CY7C1386B
CY7C1387B
512K x 36 / 1 Mb x 18 Pipelined DCD SRAM
Features
Fast clock speed: 200, 166, 150, 133 MHz
Provide high-performance 3-1-1-1 access rate
Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
Optimal for depth expansion
3.3V (鈥?% / +10%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Double-Cycle Deselect
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
鈥?Automatic power-down for portable applications
鈥?High-density, high-speed packages
鈥?JTAG boundary scan for BGA packaging version
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
inputs, address-pipelining Chip Enable (CE), burst control in-
,
puts (ADSC, ADSP and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data (DQ
a,b,c,d
) and the data
parity (DQP
a,b,c,d
) outputs, enabled by OE, are also asynchro-
nous.
DQ
a,b,c,d
and DQP
a,b,c,d
apply to CY7C1386B and DQ
a,b
and
DQP
a,b
apply to CY7C1387B. a, b, c, d each are 8 bits wide in
the case of DQ and 1 bit wide in the case of DP
.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQcand DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb, BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
The CY7C1386B/CY7C1387B are both double-cycle deselect
parts. All inputs and outputs of the CY7C1386B and the
CY7C1387B are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1386B and CY7C1387B SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
Selection Guide
200 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
166 MHz
3.4
230
30
150 MHz
3.8
190
30
133 MHz
4.2
160
30
3.0
Commercial
280
30
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
July 5, 2001

CY7C1387B相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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