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CY7C1383BV25 Datasheet

  • CY7C1383BV25

  • Memory

  • 28頁

  • ETC

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1
PRELIMINARY
CY7C1381BV25
CY7C1383BV25
512K x 36 / 1 Mb x 18 Flow-Thru SRAM
Features
Fast access times: 6.5, 7.5, 8.5 ns
Fast clock speed: 133, 117, 100 MHz
Provide high-performance 3-1-1-1 access rate
Optimal for depth expansion
2.5V (+5%) power supply
Common data inputs and data outputs
Byte Write Enable and Global Write control
Chip enable for address pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
鈥?Automatic power-down for portable applications
鈥?High-density, high-speed packages
鈥?JTAG boundary scan for BGA packaging version
鈥?/div>
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burst operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs, ad-
dress-pipelining Chip Enable (CE), Burst Control Inputs (AD-
SC, ADSP and ADV), Write Enables (BWa, BWb, BWc,
,
BWd,and BWe), and Global Write (GW).
... Asynchronous inputs include the Output Enable (OE) and
burst Mode Control (MODE). The Data Outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1鈥揇Q8 and DQP1. BWb controls DQ9鈥揇Q16 and
DQP2. BWc controls DQ17鈥揇Q24and DQP3. BWd controls
DQ25鈥揇Q32 and DQP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the immediately next READ
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1381BV25 and the
CY7C1383BV25 are JEDEC standard JESD8-5 compatible.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced single
layer polysilicon, three-layer metal technology. Each memory
cell consists of six transistors.
The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate
524,288x36 and 1,048,576x18SRAM cells with advanced syn-
chronous peripheral circuitry and a 2-bit counter for internal
Selection Guide
133 MHz
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
117 MHz
7.5
175
30
100 MHz
8.5
150
30
6.5
Commercial
200
30
Cypress Semiconductor Corporation
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3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
July 2, 2001

CY7C1383BV25相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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