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CY7C1373CV25 Datasheet

  • CY7C1373CV25

  • Memory

  • 26頁

  • ETC

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PRELIMINARY
CY7C1373CV25
CY7C1371CV25
512K x 36/1M x 18 Flow-Thru SRAM
with NoBL鈩?Architecture
Features
鈥?/div>
Pin compatible and functionally equivalent to ZBT
錚?/div>
devices
鈥?Supports 133-MHz bus operations with zero wait states
鈥?Data is transferred on every clock
鈥?Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
鈥?Registered inputs for Flow-Through operation
鈥?Byte Write capability
鈥?Common I/O architecture
鈥?Single 2.5V power supply
鈥?Fast clock-to-output times
鈥?6.5 ns (for 133-MHz device)
鈥?7.5 ns (for 117-MHz device)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?8.5 ns (for 100-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in 100 TQFP and 119 BGA Packages
Burst Capability 鈥?linear or interleaved burst order
JTAG boundary scan for BGA packaging version
respectively designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1371CV25/CY7C1373CV25 is
equipped with the advanced No Bus Latency鈩?(NoBL鈩? logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write/Read
transitions.
The
CY7C1371CV25/CY7C1373CV25
is
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the Byte Write Selects
for
CY7C1371CV25
and
BWS
a,b
for
(BWS
a,b,c,d
CY7C1373CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
ZZ may be tied to LOW if it is not used.
Synchronous Chip Enable (CE
1
, CE
2
, CE
3
on the TQFP, CE
1
on the BGA) and an asynchronous Output Enable (OE)
provide for easy bank selection and output three-state control.
In order to avoid bus contention, the output drivers are
synchronously three-stated during the data portion of a write
sequence.
Functional Description
The CY7C1371CV25 and CY7C1373CV25 are 2.5V, 512K by
36 and 1M by 18 Synchronous-Flow-Through Burst SRAMs,
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE2
CE3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256K 脳 36/
512K 脳 18
MEMORY
ARRAY
D
Data-In REG.
Q
AX
DQX
CY7C1371
X = 18:0
CY7C1373
X = 19:0
DQ
x
DP
x
X= a, b, c, d X = a, b
DPX X = a, b, c, d X = a, b
BWSX X = a, b, c, d X = a, b
OE
Selection Guide
133 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain preliminary information.
117 MHz
7.5
190
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
6.5
210
70
.
Cypress Semiconductor Corporation
Document #: 38-05236 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose, CA 95134
鈥?/div>
408-943-2600
Revised November 20, 2002

CY7C1373CV25相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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