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CY7C1354A Datasheet

  • CY7C1354A

  • Memory

  • 31頁

  • ETC

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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256K x 36/512K x 18 Pipelined SRAM
with NoBL鈩?Architecture
Features
鈥?Zero Bus Latency鈩? no dead cycles between Write and
Read cycles
鈥?Fast clock speed: 200, 166, 133, 100 MHz
鈥?Fast access time: 3.2, 3.6, 4.2, 5.0 ns
鈥?Internally synchronized registered outputs eliminate
the need to control OE
鈥?Single 3.3V 鈥?% and +5% power supply V
CC
鈥?Separate V
CCQ
for 3.3V or 2.5V I/O
鈥?Single WEN (Read/Write) control pin
鈥?Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
鈥?Interleaved or linear four-word burst capability
鈥?Individual byte Write (BWa鈥揃Wd) control (may be tied
LOW)
鈥?CEN pin to enable clock and suspend operations
鈥?Three chip enables for simple depth expansion
鈥utomatic power-down feature available using ZZ mode
or CE select
鈥?JTAG boundary scan
鈥?Low-profile 119-bump, 14-mm 脳 22-mm BGA (Ball Grid
Array), and 100-pin TQFP packages
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE
2
, and CE
3
), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (WEN). BWc and BWd
apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
There are three chip enable pins (CE, CE
2
, CE
3
) that allow the
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (Read or Write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a Write cycle is
initiated.
The
CY7C1354A/GVT71256ZC36
and
CY7C1356A/
GVT71512ZC18 have an on-chip two-bit burst counter. In the
burst mode, the CY7C1354A/GVT71256ZC36 and
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The
CY7C1354A/GVT71256ZC36
and
CY7C1356A/
GVT71512ZC18 SRAMs are designed to eliminate dead
cycles when transitioning from Read to Write or vice versa.
These SRAMs are optimized for 100% bus utilization and
achieve Zero Bus Latency錚?(ZBL錚?/No Bus Latency錚?/div>
(NoBL錚?. They integrate 262,144 脳 36 and 524,288 脳 18
SRAM cells, respectively, with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. These employ high-speed, low-power CMOS
designs using advanced triple-layer polysilicon, double-layer
metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
Selection Guide
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
Maximum Access Time
Maximum Operating Current
Commercial
Maximum CMOS Standby Current Commercial
3.2
560
30
7C1354A-166
71256ZC36-6
7C1356A-166
71512ZC18-6
3.6
480
30
7C1354A-133
71256ZC36-7.5
7C1356A-133
71512ZC18-7.5
4.2
410
30
7C1354A-100
71256ZC36-10
7C1356A-100
71512ZC18-10
5.0
350
30
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05161 Rev. *D
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 13, 2002

CY7C1354A相關(guān)型號PDF文件下載

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  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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