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CY7C1353F Datasheet

  • CY7C1353F

  • 4-Mb (256K x 18) Flow-through SRAM with NoBL? Architecture

  • 14頁

  • CYPRESS

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CY7C1353F
4-Mb (256K x 18) Flow-through SRAM with NoBL鈩?Architecture
Features
鈥?Can support up to 133-MHz bus operations with zero
wait states
鈥?Data is transferred on every clock
鈥?Pin compatible and functionally equivalent to ZBT鈩?/div>
devices
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Registered inputs for flow-through operation
鈥?Byte Write capability
鈥?256K x 18 common I/O architecture
鈥?2.5V / 3.3V I/O power supply
鈥?Fast clock-to-output times
鈥?6.5 ns (for 133-MHz device)
鈥?7.5 ns (for 117-MHz device)
鈥?8.0 ns (for 100-MHz device)
鈥?11.0 ns (for 66-MHz device)
鈥?Clock Enable (CEN) pin to suspend operation
鈥?Synchronous self-timed writes
鈥?Asynchronous Output Enable
鈥?JEDEC-standard 100 TQFP package
鈥?Burst Capability鈥攍inear or interleaved burst order
鈥?Low standby power
Functional Description
[1]
The CY7C1353F is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353F is equipped with the
advanced No Bus Latency鈩?(NoBL鈩? logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
A0,聽A1,聽A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
WE
OE
CE
1
CE
2
CE
3
ZZ
1
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Note:
1. For best鈥損ractices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05212 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 13, 2004

CY7C1353F PDF文件相關(guān)型號

CY7C1354A,CY7C1354A-133BGC,CY7C1354A-133BGI,CY7C1354A-166BGC,CY7C1354A-200AC,CY7C1354B-200AC

CY7C1353F相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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