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CY7C1352G-166AXI Datasheet

  • CY7C1352G-166AXI

  • 4-Mbit (256Kx18) Pipelined SRAM with NoBL Architecture

  • 13頁(yè)

  • CYPRESS

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PRELIMINARY
CY7C1352G
4-Mbit (256Kx18) Pipelined SRAM
with NoBL鈩?Architecture
Features
鈥?Pin compatible and functionally equivalent to ZBT鈩?/div>
devices
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Byte Write capability
鈥?256K x 18 common I/O architecture
鈥?Single 3.3V power supply
鈥?2.5V / 3.3V I/O Operation
鈥?Fast clock-to-output times
鈥?2.6 ns (for 250-MHz device)
鈥?2.8 ns (for 200-MHz device)
鈥?3.5 ns (for 166-MHz device)
鈥?4.0 ns (for 133-MHz device)
鈥?Clock Enable (CEN) pin to suspend operation
鈥?Synchronous self-timed writes
鈥?Asynchronous output enable (OE)
鈥?Pb-Free 100 TQFP package
鈥?Burst Capability鈥攍inear or interleaved burst order
鈥?ZZ鈥?Sleep Mode Option and Stop Clock option
Functional Description
[1]
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352G is equipped with the advanced
No Bus Latency鈩?(NoBL鈩? logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram
A0, A1, A
MODE
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
A
BW
B
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP
A
DQP
B
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Notes:
1. For best鈥損ractices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05514 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 10, 2004

CY7C1352G-166AXI相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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