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CY7C1351B Datasheet

  • CY7C1351B

  • Memory

  • 16頁(yè)

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351B
PRELIMINARY
CY7C1351B
128Kx36 Flow-Through SRAM with NoBL鈩?Architecture
Features
鈥?/div>
Pin compatible and functionally equivalent to ZBT鈩?de-
vices IDT71V547, MT55L128L36F, and MCM63Z737
鈥?Supports 66-MHz bus operations with zero wait states
鈥?Data is transferred on every clock
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Registered inputs for Flow-Through operation
鈥?Byte Write capability
鈥?128K x 36 common I/O architecture
鈥?Single 3.3V power supply
鈥?Fast clock-to-output times
鈥?7.5 ns (for 117-MHz device)
鈥?8.5 ns (for 100-MHz device)
鈥?11.0 ns (for 66-MHz device)
鈥?12.0 ns (for 50-MHz device)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?14.0 ns (for 40-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous Output Enable
Standard 100 TQFP and 119 BGA packages
Burst Capability鈥攍inear or interleaved burst order
Low standby power
Functional Description
The CY7C1351B is a 3.3V, 128K by 36 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351B is equipped with the
advanced No Bus Latency鈩?(NoBL鈩? logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write/Read transitions. The
CY7C1351B is pin/functionally compatible to ZBT SRAMs
IDT71V547, MT55L128L36F, and MCM63Z737.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which, when deasserted, sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 7.5 ns (117-MHz
device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
36
17
CONTROL
and WRITE
LOGIC
17
128KX36
MEMORY
ARRAY
36
DQ
[31:0]
DP
[3:0]
36
ADV/LD
A
[16:0]
CEN
CE
1
CE
2
CE
3
WE
BWS [3:0]
Mode
OE
.
Selection Guide
7C1351B-117 7C1351B-100
Maximum Access Time (ns)
Maximum Operating Current
(mA)
Maximum CMOS Standby
Current (mA)
Commercial
Commercial
7.5
375 mA
5 mA
8.5
350 mA
5 mA
7C1351B-66
11.0
250 mA
5 mA
7C1351B-50 7C1351B-40
12.0
200 mA
5 mA
14.0
175 mA
5 mA
Cypress Semiconductor Corporation
Document #: 38-05208 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose, CA 95134
鈥?/div>
408-943-2600
Revised November 19, 2002

CY7C1351B相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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