音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY7C1350B Datasheet

  • CY7C1350B

  • Memory

  • 14頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

350B
PRELIMINARY
CY7C1350B
128Kx36 Pipelined SRAM with NoBL鈩?Architecture
Features
鈥?Pin compatible and functionally equivalent to ZBT鈩?/div>
devices IDT71V546, MT55L128L36P, and MCM63Z736
鈥?Supports 166-MHz bus operations with zero wait states
鈥?Data is transferred on every clock
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Fully registered (inputs and outputs) for pipelined
operation
鈥?Byte Write capability
鈥?128K x 36 common I/O architecture
鈥?Single 3.3V power supply
鈥?Fast clock-to-output times
鈥?3.5 ns (for 166-MHz device)
鈥?3.8 ns (for 150-MHz device)
鈥?4.0 ns (for 143-MHz device)
鈥?4.2 ns (for 133-MHz device)
鈥?5.0 ns (for 100-MHz device)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?7.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP package
Burst Capability鈥攍inear or interleaved burst order
Low standby power (17.325 mW max.)
Functional Description
The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350B is equipped with the advanced
No Bus Latency鈩?(NoBL鈩? logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1350B is pin/func-
tionally
compatible
to
ZBT
SRAMs
IDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
36
17
CONTROL
and WRITE
LOGIC
17
128Kx36
MEMORY
ARRAY
36
36
ADV/LD
A
[16:0]
CEN
CE
1
CE2
CE3
WE
BWS
[3:0]
MODE
CLK
OOUTPUT
REGISTERS
and LOGIC
36
DQ
[31:0]
DP
[3:0]
OE
.
Selection Guide
-166
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
-150
3.8
375
5
-143
4.0
350
5
-133
4.2
300
5
-100
5.0
250
5
-80
7.0
200
5
3.5
Commercial
Commercial
400
5
Cypress Semiconductor Corporation
Document #: 38-05045 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised January 18, 2003

CY7C1350B相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！