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CY7C1346H-166AXC Datasheet

  • CY7C1346H-166AXC

  • 2-Mbit (64K x 36) Pipelined Sync SRAM

  • 16頁(yè)

  • CYPRESS

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CY7C1346H
2-Mbit (64K x 36) Pipelined Sync SRAM
Features
鈥?Registered inputs and outputs for pipelined operation
鈥?64K 脳 36 common I/O architecture
鈥?3.3V core power supply
鈥?3.3V/2.5V I/O operation
鈥?Fast clock-to-output times
鈥?3.5 ns (166-MHz device)
鈥?Provide high-performance 3-1-1-1 access rate
鈥?User-selectable burst counter supporting Intel
廬
Pentium
廬
interleaved or linear burst sequences
鈥?Separate processor and controller address strobes
鈥?Synchronous self-timed writes
鈥?Asynchronous output enable
鈥?Offered in JEDEC-standard lead-free 100-pin TQFP
package
鈥?鈥淶Z鈥?Sleep Mode Option
Functional Description
[1]
The CY7C1346H SRAM integrates 64K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:D]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1346H operates from a +3.3V core power supply
while all outputs also operate with either a +3.3V/2.5V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D,
DQ
D
BYTE
WRITE REGISTER
DQ
C
,DQP
C
BYTE
WRITE REGISTER
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
Q0
LOGIC
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C
,DQP
C
BYTE
WRITE DRIVER
DQ
B,
DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05672 Rev. *B
鈥?/div>
198 Champion Court
鈥?/div>
San Jose
,
CA 95134-1709
鈥?/div>
408-943-2600
Revised April 26, 2006
[+] Feedback

CY7C1346H-166AXC 產(chǎn)品屬性

  • 72

  • 集成電路 (IC)

  • 存儲(chǔ)器

  • -

  • RAM

  • SRAM - 同步

  • 2M（64K x 36）

  • 166MHz

  • 并聯(lián)

  • 3.15 V ~ 3.6 V

  • 0°C ~ 70°C

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盤(pán)

CY7C1346H-166AXC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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