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Fast access times: 5, 6, and 7 ns
Fast clock speed: 100, 83, and 66 MHz
Provides high performance 3-1-1-1 access rate
Fast OE access times: 5, 6, and 7 ns
Optimal for performance (two-cycle chip deselect,
depth expansion without wait state)
Single +3.3V 鈥?% and +10%power supply
Supports +2.5V I/O
5V tolerant inputs except I/Os
Clamp diodes to V
SSQ
at all outputs
Common data inputs and outputs
Byte Write Enable and Global Write control
Three chip enables for depth expansion and address
pipeline
Address, control, input, and output pipeline registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst
sequence)
Automatic power-down for portable applications
High-density, high-speed packages
Low-capacitive bus loading
High 30-pF output drive capability at rated access time
The
CY7C1340A/GVT71128C32
SRAM
integrates
131,072 脳 32 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE), depth-expansion Chip
Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP,
and ADV), Write Enables (BW1, BW2, BW3, BW4, and BWE),
and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and Write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the Write control inputs.
Individual byte Write allows individual byte to be written. BW1
controls DQ1鈥揇Q8. BW2 controls DQ9鈥揇Q16. BW3 controls
DQ17鈥揇Q24. BW4 controls DQ25鈥揇Q32. BW1, BW2, BW3,
and BW4 can be active only with BWE being LOW. GW being
LOW causes all bytes to be written. This device also incorpo-
rates pipelined enable circuit for easy depth expansion without
penalizing system performance.
The CY7C1340A/GVT71128C32 operates from a +3.3V
power supply. All inputs and outputs are TTL-compatible. The
device is ideally suited for 486, Pentium廬, 680 脳 0, and
PowerPC鈩?systems and for systems that benefit from a wide
synchronous data bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
Selection Guide
7C1340A-100
71128C36-5
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
5
225
2
7C1340A-83
71128C36-6
6
185
2
7C1340A-66
71128C36-7
7
120
2
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 38-05153 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised January 19, 2003
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