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CY7C133 Datasheet

  • CY7C133

  • 2K x 16 Dual-Port Static RAM

  • Cypress

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CY7C133
CY7C143
2K x 16 Dual-Port Static RAM
Features
鈥?/div>
True dual-ported memory cells which allow
simultaneous reads of the same memory location
鈥?/div>
2K x 16 organization
鈥?/div>
0.65-micron CMOS for optimum speed/power
鈥?/div>
High-speed access: 25/35/55 ns
鈥?/div>
Low operating power: I
CC
= 150 mA (typ.)
鈥?Fully asynchronous operation
鈥?/div>
Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
鈥?/div>
BUSY output flag on CY7C133; BUSY input flag on
CY7C143
鈥?/div>
Available in 68-pin PLCC
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/W
UB
, R/W
LB
), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
Logic Block Diagram
CE
L
R/W
LUB
CE
R
R/W
RUB
R/W
LLB
OE
L
R/W
RLB
OE
R
I/O
8L
鈥?I/O
15L
I/O
0L
鈥?I/O
7L
BUSY
L[1]
A
10L
A
0L
ADDRESS
DECODER
I/O
CONTROL
I/O
CONTROL
I/O
8R
鈥?I/O
15R
I/O
0R
鈥?I/O
7R
BUSY
R
[ ]
1
MEMORY
ARRAY
ADDRESS
DECODER
A
10R
A
0R
CE
L
OE
L
R/W
LUB
R/W
LLB
ARBITRA
TION
LOGIC
(CY7C133 ONLY)
CE
R
OE
R
R/W
RUB
R/W
RLB
Note:
1. CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
Cypress Semiconductor Corporation
Document #: 38-06036 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 22, 2004

CY7C133 PDF文件相關(guān)型號

CY7C143

CY7C133相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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