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CY7C1334-80AC Datasheet

  • CY7C1334-80AC

  • x32 Fast Synchronous SRAM

  • 12頁(yè)

  • ETC

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334
CY7C1334
64Kx32 Pipelined SRAM with NoBL鈩?Architecture
Features
鈥?Pin compatible and functionally equivalent to ZBT鈩?/div>
device MT55L64L32P
鈥?Supports 133-MHz bus operations with zero wait states
鈥?Data is transferred on every clock
鈥?Internally self-timed output buffer control to eliminate
the need to use OE
鈥?Fully registered (inputs and outputs) for pipelined
operation
鈥?Byte Write Capability
鈥?64K x 32 common I/O architecture
鈥?Single 3.3V power supply
鈥?Fast clock-to-output times
鈥?4.2 ns (for 133-MHz device)
鈥?5.0 ns (for 100-MHz device)
鈥?7.0 ns (for 80-MHz device)
鈥?10.0 ns (for 50-MHz device)
鈥?Clock Enable (CEN) pin to suspend operation
鈥?Synchronous self-timed writes
鈥?Asynchronous output enable
鈥?JEDEC-standard 100-pin TQFP package
鈥?Burst Capability鈥攍inear or interleaved burst order
鈥?Low (16.5 mW) standby power
Functional Description
The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1334 is equipped with the advanced No
Bus Latency鈩?(NoBL鈩? logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Write-Read transitions.The CY7C1334 is pin/functionally com-
patible to ZBT SRAM MT55L64L32P
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.2 ns (133-MHz device).
Write operations are controlled by the four Byte Write Selects
(BWS
[0-3]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
D
Data-In REG.
CE
Q
32
32
ADV/LD
A
[15:0]
CEN
CE
1
CE
2
CE
3
WE
BWS
[3:0]
CLK
OOUTPUT
REGISTERS
and LOGIC
16
CONTROL
and WRITE
LOGIC
16
64KX32
MEMORY
ARRAY
32
32
DQ
[31:0]
OE
.
Selection Guide
7C1334-133
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Commercial
Commercial
4.2
400
5.0
7C1334-100
5.0
360
5.0
7C1334-80
7.0
310
5.0
7C1334-50
10
260
5.0
No Bus Latency and NoBL are trademarks of Cypress Semiconductor.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
Document #: 38-05065 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 20, 2001

CY7C1334-80AC相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠(chǎng)商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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