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CY7C1328F Datasheet

  • CY7C1328F

  • Memory

  • 15頁

  • ETC

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PRELIMINARY
CY7C1328F
256K x 18 Pipelined DCD Sync SRAM
Features
鈥?Fully registered inputs and outputs for pipelined
operation
鈥?Optimal for performance (Double-Cycle chip deselect,
depth expansion without wait state)
鈥?256K 脳 18-bit common I/O architecture
鈥?3.3V 鈥?% and +10% core power supply
鈥?2.5V or 3.3V I/O supply
鈥?Fast clock-to-output times
鈥?2.6 ns (for 250-MHz device)
鈥?2.6 ns (for 225-MHz device)
鈥?2.8 ns (for 200-MHz device)
鈥?3.5 ns (for 166-MHz device)
鈥?4.0 ns (for 133-MHz device)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?4.5 ns (for 100-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
錚?/div>
Pentium
錚?/div>
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100-pin TQFP package and pinout
鈥淶Z鈥?Sleep Mode option
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE), depth-expansion Chip Enables (CE2 and CE2), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW0,
BW1 and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
two bytes wide as controlled by the write control inputs.
Individual byte write allows individual bytes to be written. BW0
controls DQ1鈥揇Q8 and DQP1. BW1 controls DQ9鈥揇Q16 and
DQP2. BW0 and BW1 can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write
pass-through capability allows written data available at the
output for the immediately next Read cycle. This device also
incorporates a pipelined enable circuit for easy depth
expansion without penalizing system performance.
The CY7C1328F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC standard JESD8-5
compatible. The device is ideally suited for Pentium, 680x0,
and PowerPC
廬
systems and for systems that benefit from a
wide synchronous data bus.
Functional Description
The CY7C1328F SRAM integrates 262,144x18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
Selection Guide
-250
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
-225
2.6
290
40
-200
2.8
265
40
-166
3.5
240
40
-133
4.0
225
40
-100
4.5
205
40
2.6
325
40
Cypress Semiconductor Corporation
Document #: 38-05220 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 19, 2002

CY7C1328F相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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