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CY7C1310V18 Datasheet

  • CY7C1310V18

  • Memory

  • 447.33KB

  • 25頁(yè)

  • ETC

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PRELIMINARY
CY7C1310V18
CY7C1312V18
CY7C1314V18
18-Mb QDR鈩?II SRAM Two-word
Burst Architecture
Features
鈥?Separate Independent Read and Write Data Ports
鈥?Supports concurrent transactions
鈥?167-MHz Clock for High Bandwidth
鈥?Two-word Burst on all accesses
鈥?Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @ 167MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mismatches
鈥?Echo clocks (CQ and CQ) simplify data capture in high
speed systems
鈥?Single multiplexed address input bus latches address
inputs for both Read and Write ports
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?Available in x8, x18, and x36 configurations
鈥?1.8V core power supply with HSTL Inputs and Outputs
鈥?13x15 mm 1.0-mm pitch FBGA package, 165 ball (11x15
matrix)
鈥?Variable drive HSTL output buffers
鈥?Extended HSTL output voltage (1.4V鈥揤
DD
)
鈥?JTAG Interface
鈥?On-chip Delay Lock Loop (DLL)
Functional Description
The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR
鈩?/div>
-II archi-
tecture. QDR
TM
-II architecture consists of two separate ports
to access the memory array. The Read port has dedicated
Data Outputs to support Read operations and the Write Port
has dedicated Data Inputs to support Write operations.
QDR
TM
-II architecture has separate data inputs and data
outputs to completely eliminate the need to 鈥渢urn-around鈥?the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K clock.
Accesses to the QDR
TM
-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 8-bit words (CY7C1310V18) or 18-bit
words (CY7C1312V18) or 36-bit words (CY7C1314V18) that
burst sequentially into or out of the device. Since data can be
transferred into and out of the device on every rising edge of
both input clocks (K/K and C/C), memory bandwidth is
maximized while simplifying system design by eliminating bus
鈥渢urn-arounds.鈥?/div>
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C/C (or K/K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1310V18 鈥?2M x 8
CY7C1312V18 鈥?1M x 18
CY7C1314V18 鈥?512K x 36
Logic Block Diagram (CY7C1310V18)
D
[7:0]
8
Write
Reg
1M x 8 Array
Write Add. Decode
20
Read Add. Decode
A
(19:0)
Address
Register
Write
Reg
1M x 8 Array
Address
Register
20
A
(19:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
16
Control
Logic
8
Reg.
8
Reg.
8
Reg.
CQ
CQ
V
REF
WPS
BWS
[1:0]
8
8
Q
[7:0]
Cypress Semiconductor Corporation
Document #: 38-05180 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 2, 2002

CY7C1310V18相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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