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CY7C1307V25 Datasheet

  • CY7C1307V25

  • Memory

  • 230.08KB

  • 28頁(yè)

  • ETC

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1305V25
Preliminary
CY7C1305V25
CY7C1307V25
18 Mb Burst of 4 Pipelined SRAM with QDR Architecture
Features
鈥?Separate Independent Read and Write Data Ports
鈥?Supports concurrent transactions
鈥?167 MHz Clock for High Bandwidth
鈥?2.5 ns Clock-to-Valid access time
鈥?4-Word Burst for reducing the address bus frequency
鈥?Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @167 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mis-matches
鈥?Single multiplexed address input bus latches address
inputs for both READ and WRITE ports
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?2.5V core power supply with HSTL Inputs and Outputs
鈥?13x15 mm 1.0 mm pitch fBGA package, 165 ball
(11x15 matrix)
鈥?Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?JTAG Interface
Functional Description
The CY7C1305V25/CY7C1307V25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR ar-
chitecture consists of two separate ports to access the mem-
ory array. The Read port has dedicated Data Outputs to sup-
port Read operations and the Write Port has dedicated Data
Inputs to support Write operations. QDR architecture has sep-
arate data inputs and data outputs to completely eliminate the
need to 鈥渢urn-around鈥?the data bus required with common I/O
devices. Access to each port is accomplished through a com-
mon address bus. Addresses for Read and Write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the device鈥檚 Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with Dou-
ble Data Rate (DDR) interfaces. Each address location is as-
sociated with four 18-bit words (CY7C1305V25) and four
36-bit words (CY7C1307V25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying sys-
tem design by eliminating bus 鈥渢urn-arounds.鈥?/div>
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1305V25 鈥?1 Mb x 18
CY7C1307V25 鈥?512K x 36
Logic Block Diagram (CY7C1305V25)
D
[17:0]
18
Write Write Write Write
Reg Reg Reg
Reg
A
(17:0)
Write Add. Decode
Read Add. Decode
Address
Register
18
256Kx18 Array
256Kx18 Array
256Kx18 Array
256Kx18 Array
Address
Register
18
A
(17:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
72
Control
Logic
36
Reg.
36
Reg.
18
Reg.
Vref
WPS
BWS
[0:1]
18
Q
[17:0]
Cypress Semiconductor Corporation
Document #: 38-05099 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 11, 2002

CY7C1307V25相關(guān)型號(hào)PDF文件下載

  • 型號(hào)
    版本
    描述
    廠商
    下載
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
  • 英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
  • 英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
  • 英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
  • 英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
  • 英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...

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